SU756406A1 - Device for comparing binary codes - Google Patents

Description

The invention relates to automation and computing and can be used in digital control systems for various purposes, in digital tracking systems.

A device for comparing binary codes containing a trigger with three stable states on the elements AND-NOT,

5 NAND elements, input buses, unequal element [1].

The disadvantage of this device is low speed, due to the fact that the codes are fed to its inputs in the form of serial codes and are analyzed sequentially discharge by discharge, in addition, it can only be used in digital control systems with relay control.

The closest technical solution to the proposed is a device for comparing binary codes containing registers, a node issuing, a group of elements And, an adder, and the inputs of the first and second registers are connected to the input buses of the device, and their outputs - with information inputs of the elements of the first and second groups exits

2

. which are connected to the inputs of the adder, the outputs of which are connected to the inputs of the third register, the outputs of which are connected to the inputs of the output unit, the control inputs of the elements of the first and second groups are connected to the first control bus of the device, the first control input of the issuing node is connected to the second control bus of the device 12)

The purpose of the invention is to improve the accuracy of the device.

This is achieved by the fact that the device for comparing binary codes containing registers, a node issuing, a group of elements And, an adder, and the inputs of the first and second registers are connected to the input buses of the device, and their outputs - with information inputs of the elements of the first and second groups, the outputs of which are connected to the inputs of the adder, the outputs of which are connected to the inputs of the third register, the outputs of which are connected to the inputs of the supply unit, the control inputs of the elements of the first and second groups are connected to the first control bus of the device, ne vy input control dispensing assembly

3 756406

connected to the second control bus set- 1 0

1.1, AND, OR, NOT elements added

what is the way out? the sign rank of the first register - 1 1

Pa connected to the first input of the first element And through the first element NOT - with the first input of the second element And, the output of the sign bit of the second register is connected to the second input of the first element And and through the second element of NO - the second input of the second element And, the output of the sign bit of the third The 10th register is connected to the third input of the second element AND, and through the third element NOT to the third input of the first element AND, the outputs of the elements AND are connected to the inputs of the OR element, the output of which is connected to the second 15 control input of the output unit.

The drawing shows a block diagram of the proposed device.

The device consists of registers 1 and 2, a group of elements And 3 and 4, an adder 5, a register 6, an output node 7, elements NOT 8-10, elements 11 and 12, an element OR 13, control buses of device 14 and 15 .

The device works as follows.

The compared codes are sent to the registers 25 1 and 2. The control signal received via the control bus 14 opens the elements I of the first and second groups 3 and 4 and the codes go to the adder 5 for comparison. The result of the comparison is recorded in register 6. 30

Then the sign bits of registers 1, 2 and 6 are fed to the inputs of the elements NOT 8-10, respectively. The signals from the outputs of the HE elements 8 and 9 and the sign bit of the register 6 are fed to the inputs of the And 31 element, and the signals from the output of the HE element 10 and the sign bits of registers 1 and 2 are fed to the inputs of the And 12 element, the signals from the outputs of the And 11 elements and 12 are fed to the inputs of the element OR 13. The signals at the output of the element OR 13 are formed 40 in accordance with the equation

where Υ is the output signal;

- the signal at the input element is NOT 8; 45

X ^ - the signal at the input of the element is NOT 9;

X ^ - the signal at the input of the element is NOT 10.

The signal from the output element OR 13 enters

to the input node 7 issues each digit of which pogo is an machine without memory, working 50 scm according to following table truths: 7 Have 0 0 0 0 0 0 one 0 55 0 one 0 0 0 one one 0 one 0 0 0

four

eleven

0 1

eleven

Here is the signal on the control bus 15 (for Ζ = 1, the output is allowed), Υ is the signal from the output of the element OR 13, is the output

1st digit discharge unit. If \ - 0, i.e. there is no overflow, then the signal from the information

the input is unchanged transmitted to the input of the shopping center. If 1, then there is an overflow and a signal 1 is generated at the output, i.e. The code 111 ... 1 is output from the circuit outputs, which corresponds to the maximum control action. The sign of the mismatch code can be obtained by simply inverting the sign of the result, which is obtained in the case of overflow.

The proposed device maintains performance when the mismatch codes, modulo large 0, 111 ... 1, which is important when used in digital control systems.

Claims (1)

Claim A device for comparing binary codes containing registers, a node issuing, a group of elements And, an adder, the inputs of the first and second registers are connected to the input buses of the device, and their outputs - with information inputs of the elements of the first and second groups, the outputs of which are connected to the inputs of the adder The outputs of which are connected to the inputs of the third register, whose outputs are connected to the inputs of the output unit, the control inputs of the elements of the first and second groups are connected to the first control bus of the device, the first control input of the node in problem is connected to the second control bus device, characterized in that, in order to improve the accuracy of the device, the elements AND, OR, NOT are entered into it, and the output of the sign of the first register is connected to the first input of the first element AND and through the first element NOT the first input of the second element And, the output of the sign bit of the second register is connected to the second input of the first element And through the second element NOT to the second input of the second element And, the output of the sign bit of the third register is connected to the third input of the second ele And through the third element NOT - with the third input of the first element AND, the outputs of the elements AND are connected to the inputs of the element OR, the output of which is connected to the second input of the control site issuance.