SU635485A1 - Binary number comparing arrangement - Google Patents

Description

The invention relates to automation and computer technology. And can be used to implement technical means of automation. And a computer to compare two numbers synchronously received in a direct, m binary code, in which the sign is contained in the lth digit and the numbers arrive. Junior discharge ahead. A device for comparing binary numbers is known, which contains a three-stable TRIGGER on NAND elements, an element of une. Values, and elements 1. The disadvantages of the known device are narrow functionality, because it allows you to compare numbers only by equality. The closest technical solution to the invention is a device for comparing binary numbers containing a three-stable trigger on AND-NOT elements, an inequality element, AND-NOT, NOT, AND, OR elements, and one of the inputs of the first AND-NOT element is connected to one of the inputs of the inequality element and is connected to the first input bar, one of the inputs of the second element is NOT connected to the other input of the inequality element and connected to the second input bus, the other inputs of the first and second elements of the NAND and the input of the element are NOT connected to you The disparity element moves the outputs of which are connected to the first, second, and third information inputs of the three-stabilized trigger, and the trigger installation inputs are connected to reset button 2. However, this device has narrow functionality due to the fact that it does not allow comparison of the numbers with the sign. The purpose of the invention is to clarify the functionality of the device for comparing binary numbers and the implementation of the algebra Comparison operation. This goal is achieved by the fact that in the device the first and third outputs of the three-stable trigger are connected to the inputs of the AND element, the output connected to the input of the third AND-NOT element and the first PI1LI element whose outputs are connected; and the second inputs of the fourth NAND element, the third input of the fourth PI element is NOT connected to the third output of the three-stable trigger and to one of the inputs of the second OR element, the other input of which is connected to the output of the inequality element. The other input of the first element OR is connected to the second input bus, the other input of the third AND-NOT element to the first input bus, and the outputs of the fourth AND-NOT element and the second OR element to the first and second output buses of the device comparison of binary numbers and to the inputNM of the fifth IS-NOT element, the output of which is connected to the third output cable, another device for comparing binary numbers.

The functional scheme of the device for comparing the two, ich, members is shown in the drawing.

The device contains the element ./ nonequivalence, Input wires, us 2 and 5, the element NOT 4, the elements AND-NOT 5, 6, the elements AND-NOT 7, 8, 9 of the three-sided .gger, width 10 reset, the element 11, the element OR 12, the elements AND-NOT / 5, 14, 15, the element OR 16, the output shi.ny 17, il8 and 19.

The device works as follows.

In the INITIAL state, on the bus “at 10 reset, a logic level of zero is applied, and as a result, the output of the AND-NO element 9 is set to the zero logical level, and, at the outputs of the AND-NE elements 7 and 8, one, n, and logical levels . On the output bus 75 there is a zero logic level, and on the output buses 17 and 19 there is an ED | I, n; ich logical logic levels. For the input buses 2 and 5 of the device, direct last-user-binary binary codes of the compared numbers are supplied, “Achina with Minor. Discharge. The matching of the compared codes at the output of element 1, unea-1BNOn.acon "spine, appears zero. Logical level, and at the outputs of AND-NOT elements 5, 6, and NOT 4 - one, nothing logical levels, resulting in logical levels (At the outputs of the AND-HE elements 7, 8, 9, and, at the output lines 17, 18, 19, they are not changed.

The bus input bus 2 is supplied. The signal is zero, and the input bus 3 is single. In this case, at the output of the "equal-value" element, a single loopic level is formed, which opens the AND-NOT elements 5 and 6. The zero logical levels from the outputs of the HE 4 elements and the AND-NOT 6 form the single logical levels of the outputs elements AND-NOT 5, 9, and zero logic level at the output of the element AND-NOT 7. Next, a device for comparing. Binary numbers function similarly to an analogous pattern (1–1) tact, where n is the size of the range of the codes being edited, compares the numbers to their absolute values. NRI | L | / ,, where A B is the supplied input bus 2: and 5 codes of the numbers being compared, the output of the NAND 7 element has a zero logic level, and on the outputs of the element B the IS-NES S and P are unit logic levels. When A B “a” of the output of the AND-NE element 9, the zero logic level is terminated, and at the outputs of the elements 7 and 5 single logic levels are applied; iri A B and the output of the NAND element is an 8-zero logical level, and at the outputs of the NAND elements .7 and 9-unit logical levels. On the yy-1m cycle, the input tires 2 and 5 are signed digits of the codes of the numbers being compared.

For example, suppose that, B and L is the direct code of the negative Psl, and B is the direct code of the forward position of the 0th number, i.e., the "-iM clock input Awl 2 receives a single logical urO: V. Den, and an input | S111u 3 - (zero logical level. In this case, the output of the OR element .12 has a single logical level, and the output of the element V. JI - Zero. Logical level, and 1 at the output of the element. AND-NO 13 - a single logical level. Due to the presence of a single. logical Zfovn at the output of element 9 at the output of element 14 and, accordingly, on the output bus / 7 a zero logical level is formed, and at the output of the OR 16 element and on the output awl 18 - a single logical pO: value. The single logical level is also at the output of the AND-15 element and accordingly la. output bus 19. The presence of a zero logical level on the output slot 17 indicates that. A and B and a zero logic level is correspondingly either on the output slot 18 or on the output bus 19.

I. Use of the invention allows to expand the functionality of the device by implementing an algebraic comparison.

Claims (2)

1. Marr. E. EI. Simple logic circuits for sraaneki binary numbers. Elektrokika, t. 45, No. 7, .M., “Mir, 1972, p. 61, R.I. one. 2. USSR author's certificate number 485445, cl. G 06 F 7/04 1974.