SU1049951A1 - Device for receiving and processing multicase coded data - Google Patents

Abstract

A device for receiving and processing information in multi-register codes containing the first and second registers, the first decoder, the parity check unit, the first AND element, and the first impulse generator, which in order to improve the reliability and speed of the device, a group is entered into it AND elements, memory block, power element, OR elements, second, third and fourth AND elements, triggers, NOT elements, second and third pulse shaper, counters, second and third decoders, the first inputs of the device connected to the input of the first and second elements OR, and with the first inputs of the corresponding elements AND group, the output of elements AND of the group, except the last, are connected respectively to the first inputs of the first register, the output of the last of the elements AND group is connected to the first input of the third element OR, the output of which connected to the second input of the first register, and the outputs of the first register are connected to the first common input of the memory unit and the inputs of the first decoder, the first output of which is connected not directly to the first inputs of the the fourth and fifth elements OR and the single input of the first trigger and through the first 1GE element to the first input of the first element AND, the second output of the first decoder is connected directly to the first input of the sixth element OR, the second input of the fifth OR element, single input the second trigger and through the second element is NOT with the second input of the first element AND, the third output of the first daaifratora is connected directly to the second inputs of the fourth and sixth elements OR and the single input third. its trigger and, through the third element NOT, to the third input of the first element, And, p. No., the outputs of the flip-flops, are connected to the second address. Entry ® of the memory block, the output of which is connected (L to the information input of the second register, the outputs of which are the first outputs device and connected to the inputs of the parity check unit, the output of which is connected to the single input of the fourth flip-flop and the fourth input of the first element I, the direct output of the fourth 4 flip-flop is connected to the fault input of the first register and the zero CO input The first trigger, the output of the first element, AND is connected to the one input of the fifth trigger, the zero SP input of which is the second input of the device, the direct output of the fifth trigger is connected to the second output of the device and connected to the counting input of the second counter, the inverse output n This trigger is connected to the input of the second element I, the fourth output of the first decoder through the fourth element is NOT to the second input of the second element AND, the output of which is connected to the second input of the first element OR and to the second input of the third element nta OR, exit first. element OR is connected to the inputs of the first and second shaper

Description

pulses, the output of the first pulse driver - f. the single input of the sixth flip-flop, the direct output of which is connected via the third pulse shaper to the input e; 1 delay; with the fault input of the second register and the zero input of the fourth flip-flop; the output of the delay element is connected to the control input of the pg1mti unit; the inverse output of the sixth trigger is the second inputs of the AND group elements and the first input of the third AND element, the second input of which is the third input of the device, the output is connected to the first input of the seventh OR element, the output of the second pulse generator connected to the first input of the fourth element And, the second input of which is connected to the pr NMM output of the eighth trigger and

the third input of the second element And,

the output of the seventh element OR - with a single input of the seventh trigger, the zero input of which is connected to the output of the fourth element I, the direct output of the seventh trigger is connected to the third output of the device, the inverse output - with the fourth input of the second element I, the output of the second element OR - with a reset the input of the first counter. The outputs of which are connected to the inputs of the second decoder, the output of the second. Decoder - with a single input of the eighth trigger, the inverse output of which is connected to the third inputs of the elements And groups, the outputs of the second with the chetchik - with the inputs of the third decoder, the output of which is connected to the second seventh element OR, the zero input of the eighth trigger and the reset input of the second counter.

The invention relates to automation and telemechanics and can be used to receive information transmitted in multi-register codes.

A device for inputting information is known, comprising a register, elements AND and OR, a pulse generator, a decoder, triggers, one-shot 1.

However, such a device provides receptions and processing. Information only in non-register codes and cannot be used when pairing with information carriers in multi-register codes, for example, MTK-2,

which limits its functionality and use.

The closest to the invention to the technical essence is a device for receiving information, containing a transmission control unit, the inputs of which are connected to the inputs of the device, the decoder, the input of which is connected to the first input of the device, and through the AND-NOT element to the nepBHiyi input of the AND element, the output of which connected to the first input of the pulse generator, the first output of which is connected to the first input of the pulse distributor, the second input of which is connected to the second input of the device, the second input of the device connected to the second input of the pho pulse impulse; The second output of which is connected to the first output of the device, the second output of which is connected to the output of the transmission control unit, the second input of the transmission control unit is connected to the third input of the device, the output to the first display element, the output of the decoder is connected to the first inputs of the ti registers, the outputs which are connected to other elements of the display, n-1 outputs

0 pulse distributor connected to the second inputs of the registers, the n-th output of the pulse distributor is connected to the second input of the element And, the output of which is connected to

with the second input of the h-ro register C2j.

However, the known device does not provide reception of information from a source of fi multi-register codes with its conversion to non-register

0 codes needed to display

on the screen of the indicator, for example, when it is supplied with symbols in three-register codes MTK-2 and transformed into symbols according to GOST 13052-74 for displaying not on the screen of a CRT. In addition, the well-known device does not form separation zones (groups of space characters) visible on the indicator screen between received different texts, which makes it difficult to read and separate received texts from each other when displaying information on the indicator screen, increases reading and analysis time. Noah onepafTopOM information.

The use of a known device for receiving information in multi-register codes requires: the use of additional interface devices and conversions, which are included between the source of information, the known device and the indicator, which complicates the process of receiving information and reduces the accuracy of the entire complex of the device as a whole. The purpose of the invention is to increase the speed and reliability of the device by providing reception of information in multi-register codes, converting it into registry-free codes for displaying an indicator on the screen with the division of the received text values from each other by groups of the symbol Space. The goal is achieved in that the device for receiving and processing information in multi-register codes, containing the first and second registers, the first decoder, the parity check unit, the first And element, and the first impulse generator, has been introduced an elementary group. OR, second, third and fourth elements AND, elements NOT, second and third pulse shapers, counters, second and third decoders, the first inputs of the device are connected to the inputs of the first. the second OR elements and the first inputs of the corresponding I. group elements, the outputs of the AND elements of the group except the last one are connected respectively to the first inputs of the first register, the output of the last of the AND elements of the group is connected to the first input of the third OR element, you-. the stroke of which is connected to the second input of the first register, the outputs of the first register are connected to the first address input of the memory unit and the inputs of the first decoder, the first output of which is connected directly to the first inputs of the first. counter, the fourth and fifth ele-t cops OR and the single input of the first trigger, and through the first element NOT to the first input of the first element AND, the second output of the first de encoder is connected directly to the first input of the sixth element OR, the second input of the fifth element OR, unit input of the second trigger and through the second element is NOT with the second input of the first element AND, the third output of the first decoder is connected directly to the second inputs of the fourth and sixth elements OR and one input one third of its trigger and through the third ele NOT is with the third input of the first element I, the direct inputs of the flip-flops are connected to the second address input of the memory block, the output of which is connected to the information input W6t oro of the register, the outputs of which are the first outputs of the device and connected to the inputs of the parity checker, output which is connected to the single input of the fourth trigger and the fourth input of the first element I, the direct output of the fourth trigger is connected to the fault input. the house of the first register and the zero input of the sixth flip-flop, the output of the first element I is connected to the single input of the fifth flip-flop, the zero input of which is the second input of the device, the direct output of the fifth trigger is connected to the second output of the device and connected to the counting input of the second counter, the inverse output of the first flip-flop is connected to the first input of the second element AND, the fourth output of the first decoder through the fourth element NOT to the second input of the second element AND, the output of which is connected to the second input of the first element OR the second input of the third element OR, the output of the first element OR is connected to the inputs of the first and second pulse shapers, the output of the first pulse shaper is connected to the single input of the sixth trigger, the direct output of which is connected through the third driver and pulses, to the input of the delay element, with a second input fault. register and zero input of the fourth trigger; the output of the delay element is connected to the control input of the memory unit; the inverse output of the sixth trigger is connected to the second inputs of the AND elements of the group and to the first input of the third element AND whose second input is the third input of the device; the first input of the seventh element OR, the output of the second pulse driver is connected to the first input of the fourth element AND, the second input of which is connected to the direct output of the eighth trigger — and the third input of the second element And, the output of the seventh element nta OR is connected to the single input of the seventh trigger; pa, the zero input of which is connected to the output of the fourth element, And, the direct output of the seventh trigger is connected to the third output of the device, the inverse output to the fourth input of the second element, And, the output of the second element OR, to the reset the input of the first counter, the outputs of which are connected to the inputs of the second decoder, the output of the second decoder with a single input of the eighth trigger, the inverse output of which is connected to the third inputs of elements And groups / outputs of the second counter - input E third decoder output is connected to the second input of the seventh OR gate, a zero-g WMOs house and eighth flip-flop reset input of the second counter. FIG. 1 shows a block diagram of the proposed device; in fig. parity check block diagram. The device contains (Fig. 1) the first inputs Ij-1, a group of 2 elements AND 3, 3 and. 3, the first register memory block 5, the second register 6, the first outputs 7 of the device, the third element OR 8, the first decoder 9 the sixth , fourth and fifth elements .OR 10-12 first, second and third triggers 13-15, element 16 delay parity block 17, fourth, trigger 18, first element OR 19, third, second and first elements NOT .20- 22, the first element And 23, the fifth trigger 24, the second output 25 and the second input 26 of the device, the first driver 27 of the pulse n to a given front, the second driver 2 8 pulses on the leading edge, the sixth trigger 29, t Zetiy element I 30, the fourth element And 31, the third driver 32 impulses n the leading edge, the seventh element OR 33, the seventh trigger 34 the third output 35 of the device, the third input 3 of the device, the element OR 37, the first counter 38, the second decoder 39, the second counter 40, the third decoder 41, the eighth trigger 42, the second element 43, the fourth element NOT 44.,. The control unit 17 for evenness (Fig. 2) contains AND 45, OR-HE 46 elements, providing even (odd) counting using the direct and inverse codes. The memory block is made in the form of a random-access memory device, for example, of the core-discharge type, with the addressing principle of selecting information, which is determined by the cores being wired by the cores. . The device works as follows. At the operator's command, a signal is fed to the input 36 of the device that is fed to the second input of element 30, the first input of element 30 is supplied with a high potential from the inverse output of trigger 29, and element 30 opens and the signal from its output through element 33 sets in one state the trigger 34, the output of which at the output 35 of the device issues with a potential signal of the request to the source of information. In the presence of this signal, the source of information forms a message in the three-register code of the MTC-2, which contains three groups of character codes and three. Register features - Russian, Latin, Digit. Each message consists of consecutively received parallel codes of register features and symbols, and the codes of register features follow immediately before the codes of the corresponding group of characters or codes of single characters. Each received code contains six bits: five information bits and one sync bit. In this case, the code of the register feature Russian coincides with the code for the absence of information and has the following form: the value of five information bits is logical About, the value of synchronization bit The bits of the input logic code 1, 2, 4, 5 and the synchronization bit .6 arrive to the device at the inputs a and bit 3 - at the input ig to the corresponding elements from group 2, prepared for opening, with potential signals from the inverse outputs of the triggers 29 and 42, at the inputs of the elements OR 19 and 37. Through the elements AND 3, 3, 3 and OR 8, the input code is written in register 4. E ement OR 19 detects the presence of a logic 1 in any of the six rows of code bits, i.e. detects the arrival of 3 device character codes or register signs element OR 37 detects the arrival of the device codes containing a logical 1 in any of the five information bits. From the outputs of register 4, the code is fed to the first address inputs of memory block 5 and the inputs to the decoder {b.a 9. The decoder 9 analyzes and decodes only the codes of the register features and the character code of the space character. The signal at its first output corresponds to the register attribute Russian, sets the trigger 13 to one state and inserts triggers 14 and 15 through the elements OR 11 and 12. The signal at the second output of the decoder 9 corresponds to the register sign Latin, setting it to one trigger 14 and zeroing through the elements OR 10 and 12 triggers 13 and 15. The signal on the third time of the decoder 9 corresponds to the Record Digit feature, sets the trigger -15 to one state and zeroes through the elements OR 10 and 11 triggers 13 and 14. Taim about azom code supplied registovogo feature decoded deshifatorom 9, stored on one rigger from 13-15 and stored thereon arrival of the next code reistrovogo characteristic. The state of register bits 4 and riggers 13-15 determines the access code at the inputs of memory block 5, with the help of which characters can be transformed from MTK-2 codes to characters in GOST codes. At each address in the memory block 5, a GOST code of the corresponding symbol is pre-recorded. The case codes for MTK-2 are not informational, they are not displayed on the indicator screen, so they are converted into a zero code using memory block 5. The reading of the GOST codes from memory block 5 at a given address defined by the MTK-2 input code is performed as follows. . : Upon receipt and subsequent dropping of each input MTK-2 code, the signal at the input of the element OR 19 is output and removed. At this, driver 28 generates a pulse on the leading edge of the input information, which is fed to element 3, however, the latter remains closed, since trigger 42 is in the zero state. When the MTK-2 input code is dropped, the shaper 2 generates a pulse on the trailing edge of the information, which sets trigger 29 into one state. The trigger 29 captures the moment of reset of the input code and closes the elements of the FROM. The signal from the direct output of the trigger 29 is fed to the driver 32, the pulse from the output of which confirms (establishes) the zero position of the trigger 18 and through the delay element 16 is fed to the read input of the 5 p & m unit. Since the address corresponding to the input MTK-2 code is set at the address inputs of the memory block, the GOST code of the corresponding character is read from the memory block at this address. From the outputs of memory block 5, the GOST code is written into the output register b, from the outputs of which is fed to the outputs 7 of the device and the parity check block 17. In block 17, the read GOST code is checked by parity and, with correct parity, the signal from the output of block 17 sets the trigger state to one. 18, which records the presence of correct information in register 6. Trigger 18 sets register 4 and trigger 29 to zero. In addition, the signal from unit 17 output is fed to the fourth input of element 23, to the other inputs of which through elements 20-20 signals come from the outputs of the decoder 9. In the event that the code of the register sign arrives at the inputs 1 | -1 of the device, which is converted into a zero code in memory block 5 and is not displayed on the screen, the corresponding decoded signal from the output of the decoder 9 through the corresponding vell NOT 20-22 closes the element AND 23. In the event that inputs 1 (-1 of the device receive the MTK-2 code, which is converted into the corresponding symbol in the GOST code in memory block 5, there are no signal at the outputs of the decoder 9. and the AND 23 element is opened by a signal from the output of the parity control unit 17. The signal from the output of the AND 23 element sets the trigger 24 to one state. The single state of the trigger 24 indicates that the code of the character is in register b accept external device for displaying ind ikatora. The corresponding signal from the direct output of the trigger 24 is fed to the output 25 to an external device. This code receives the code from the outputs 7 of the register 6. At the same time, the signal from the output of the trigger 24 is fed to the counter 40, which counts the number of characters issued | into an external device. After receiving from the outputs of the register b the character code in GOST, the external device issues a response signal about receiving the information, which is fed to the input 26 and resets the trigger 24 to the zero state. The device returns to the initial state and receives the following MTK-2 code on the inputs 1 messages. After receiving and converting all the codes of this message to the inputs. the device receives sequentially a group of codes of the register characteristic Russian, containing a logical 1 only in the synchronization bit. This group is. There is a separation between messages. The number of codes in this group is arbitrary, but not less than the given value. These codes are similarly written to register 4 and decoded by decoder 9, which generates signals at its first output. These signals are counted by the counter 38. In the case when the codes of the register feature Russian are not separating between messages, i.e. their number in the group is 1 or less than the specified P, followed by a register character, the character code through the element OR 37 has zeroed the counter 38. In the case when the number of signals received by the estimator 38 is equal to the specified P, the output of the decoder 39 is generated which establishes the p single state of trigger 42, trigger 42 removes the signal from the inputs of the elements of R 3 and prohibits it from recording the next information code in register 4 from the inputs l | -lg of the device. In addition, the trigger 42 prepares for opening the elements And 43 and 31, Codes of register signs Russian separation area.

as described above, are converted in the memory unit 5 into a steering code, while the trigger 24 remains during reception and conversion, these codes are in the zero position, due to the external device does not accept information from the output buses 7 for display. converting a given number P. of codes of register features of the Russian dividing section, the outputs of the device receive the following code, which through the element OR 19 and formed. The pulse 28 on the leading edge fails element I 31, prepared for opening by trigger 42. The signal from the output of element 31 sets the trigger 34 to zero, which removes the information request signal from the output 35 of the device, the external device holds the next code on the inputs until the next display request information signal. In this case, all the inputs of the AND 43 element are supplied with potential signals: from the output of the HE 44 element, from the direct output of the trigger .42, from the inverse outputs of the trigger 24 and 34. The AND 43 element opens and the signal from its output is fed to the input of the OR element 8.

The element OR 8 provides the formation of a logical 1 in the third bit of the MTK-2 code, which corresponds to the space character code for logical O in the remaining bits. The signal from the output of element 8 is supplied to the input of the third bit of datalog 5, which fixes the character code of the Space in MTK-2. This code is decoded by the decoder 9, from the fourth output of which a Space signal is output, which closes the AND 43 element through the NOT 44 element, and the signal from the output of the OR element 19 is removed. Shaper 27 generates a pulse on the falling edge of the information and the written off process repeats.

In this case, from the memory block 5 into the register 6, the Space character is read in the GOST code, which is displayed

on the screen of the indicator. After receiving this code, the trigger 24 is reset by the external device, register 4 is removed, the signal from the fourth output of the decoder 9 is opened, the element 44 is again opened, and potential signals are given to all inputs of the AND 43 element. At the output of the element And 43 a signal is formed and the process is repeated, i.e. there is a periodic formation and expiration of the group of characters Space in GOST into the external device, providing a visual separation of received messages. The number of characters output to the external device is counted by the counter 40. In the case when the number of characters received by the external device is equal to, for example, equal to the number of characters in the indicator line, a signal is generated at the output of the decoder 41. This signal sets. the counter 40, the trigger 42, and the trigger 34 are in one state. The trigger 42 closes the AND 43 element and the issuing of the Space characters is terminated. In addition, the flip-flop 42 permits writing the code held at the inputs l; j -Ig by an external device. Through the elements 43 to the register 4. T {eigger 34 fits. At output 35, an information request signal to an external device, which resets the MTK-2 code of the next message symbol from bus 1, while the pulse former 27 generates a pulse along the rear-front that reads the corresponding GOST code from the memory block 5 and the described process repeats.

The proposed device ensures the reception of information in multi-register codes, their conversion to non-register and the formation of separation plots between messages when they are displayed to the operator on a CRT screen, which increases its reliability and reduces the time for visual processing of information.

Recline

Claims (1)

DEVICE FOR RECEIVING AND PROCESSING INFORMATION IN MULTI-REGISTRATION CODES, containing the first and second registers, the first decoder, the parity block, the first element And and the first pulse generator, characterized in that, in order to increase the reliability and speed of the device, a group is introduced into it AND elements, memory unit, delay element, OR elements, second, third and fourth AND elements, triggers, NOT elements, second and third pulse shapers, counters, second and third decoders, the first inputs of the device being connected s vhodat with the first and second OR elements and to the first inputs of AND gates corresponding group exit elements and the group except the last one, are connected respectively to the first "! inputs of the first register, the output of the last of the AND elements is connected to the first input of the third OR element, the output of which is connected to the second input of the first register, ⁷ outputs of the first register are connected to the first address input of the memory block and the inputs of the first decoder, the first output of which is connected directly to the first the inputs of the first counter, the fourth and fifth elements OR and the single input of the first trigger and through the first element NOT - with the first input of the first element And, the second output of the first decoder is connected directly with the first input of the sixth OR element, the second input of the fifth OR element, the single input of the second trigger and through the second element NOT with the second input of the first AND element, the third output of the first decoder is connected directly to the second inputs of the fourth and sixth elements OR and single the input of the third trigger and through the third element NOT with the third input of the first element AND, the direct outputs of the triggers are connected to the second address input of the memory block, the output of which is connected to the information input of the second register, the output which are the first outputs of the device and connected to the inputs of the parity block, the output of which is connected to a single input of the fourth trigger and the fourth input of the first element And, the direct output of the fourth trigger is connected to the reset input of the first register and the zero input of the sixth trigger, the output of the first element And is connected to the single input of the fifth trigger, the zero input of which is the second input of the device, the direct output of the fifth trigger is connected to the second output of the device and connected to the counting input of the second of the counter, the inverse output of the fifth trigger is connected to the input of the second AND element, the fourth output of the first decoder through the fourth element is NOT to the second input of the second AND element, the output of which is connected to the second input of the first OR element and with the second input of the third OR element, the output is first -, th element OR connected to the inputs of the first and second shaper Sl · .. 1049951 pulses, the output of the first pulse shaper - 4: by a single input of the sixth trigger, the direct output of which is connected through the third pulse shaper to the input of the delay element, with the reset input of the second register and the zero input of the fourth trigger, the output of the delay element is connected to the control input blo ^! memory, inverse output of the sixth trigger — with second inputs of AND elements of the group and with the first input of the third AND element, the second input of which is the third input of the device, the output is connected to the first input of the seventh OR element, the output of the second pulse shaper is connected to the first input of the fourth AND element , the second input of which is connected to the direct output of the eighth trigger and the third input of the second element AND, the output of the seventh element OR - with a single input of the seventh trigger, the zero input of which is connected to the output of the fourth And, the direct output of the seventh trigger is connected to the third output of the device, the inverse output is with the fourth input of the second AND element, the output of the second OR element is with the reset input of the first counter, the output of which is connected to the inputs of the second decoder, the output of the second decoder is with the single input of the eighth a trigger whose inverse output is connected to the third inputs of the AND elements of the group, the output of the second counter - to the inputs of the third decoder, the output of which is connected to the second input of the seventh OR element, the zero input of the eighth trigger and reset input of the second counter. ¹