SU1157545A1 - Information input device - Google Patents

Description

The second and fourth elements And the output of the fourth element And is connected to the second input of the fourth element OR, the output of which is connected to the first input of the fourth trigger, the output of which is connected to the second input of the third element And, the second output of the first trigger And connected, output; the second trigger is connected to the third input of the fifth element I, the output of which is connected to the second

the fourth trigger input, the output of the sixth element I is connected to the second input of the third trigger, the output of which is connected to the third input of the first element I, the second and third outputs of the first decoder are connected to the corresponding inputs of the element whose output is connected to the fourth input of the first element I, whose output connected to the second input of the first register.

The invention relates to computing and can be used to read information from punched tapes. A device for inputting information is known, comprising a linking unit, a synchronization unit, an amplifier unit, a register, a key unit, a memory unit, 1 J pulse generators. However, this device provides input of texts printed on the carrier in multi-register codes, separating the various input texts each, Separated by dividing areas containing groups with the SPACE character, which limits the functionality of the device, complicates the subsequent decoding and reading of texts. The closest in technical essence to the invention is an information input device comprising a reading unit, an amplifier unit, a register, a switch, pulse formers at the leading and trailing edges, AND, OR, trigger elements, synchronization and control units 2. When entering information in multi-register codes, for example, in three-register MTK-2 codes, in a known device, the Russian register code containing a single value only in the sync bit and unsealed on one Kfe of the carrier does not differ from the group s such codes, placed in several rows carrier. In multi-register codes, the register feature code is perforated on one line of the carrier before the codes by the symbol and indicates to which register — Russian, Latin or digital — these symbols belong, which ensures their appropriate decryption. The group of codes of the Russian register corresponds to the separation section between different texts. On one medium and is not for the subsequent text a sign of the Russian register, but in a known device can be perceived only as a register characteristic RUSSIAN. This can lead to incorrect decoding of the following text. In addition, when entering several texts from one medium separated by groups of Russian register codes into a memory block, the known device does not ensure the formation of dividing sections between texts in the form of corresponding groups of SPACE characters from their entries into a memory block. At the same time, the entered texts are not separated from each other, which complicates subsequent reading and can lead to incorrect interpretation. forging the information received. Since in the known device the codes of the dividing section are not converted into SPACE characters, as a result, a large amount of memory is filled with useless information in the form of Russian register codes. To avoid this, in a known device, the information is interrupted at the separation points, followed by a shift to the next side of the text and restarting it, which reduces the speed of the device, increases the time of information input. Thus, the disadvantage of the known device lies in its speed, accuracy and reliability of entering information in multi-register codes. The purpose of the invention is to increase the speed and accuracy of devices. The goal is achieved in that the device for entering information contains a reading unit whose outputs are connected to the inputs of an amplifier unit whose outputs are connected to the inputs of the first OR input, the first register whose outputs are connected to the inputs of the first group. the switch, the outputs of which are the outputs of the device, the first and second pulse drivers, the first AND element, the first trigger, the second register, the second switch, the encoder, the first and second, decoders, counter, second, third and fourth triggers, element OR NOT, second, third and fourth elements OR, second, third, fourth, fifth and sixth elements AND, first, second, third, fourth and fifth the delay elements, the outputs of the amplifier unit are connected to the inputs of the first decoder, the inputs of the first group of the second OR element, and the inputs of the third OR element, the outputs of the second OR element are connected to the inputs of the second register group, the outputs of which are connected to the group inputs of the second switch with the inputs of the First Register group, the output of the first element OR is connected to the inputs of the first and second pulse formers, the output of the first driver of the pulses is connected to the input of the first delay element, the output of which is connected to the first input of the first element AND at the input of the second delay element. connected to the input of the third delay element and with the first inputs of the second and third elements And, the output of the third element And connected to the input of the first switch, the output of the second element And connected to the input of the encoder The outputs of which are connected to the inputs of the second group of the second OR element, the output of the third delay element is connected to the first input of the first register, the output of the second pulse shaper is connected to the input of the fourth delay element, the output of which is connected to the input of the fifth delay element, the input of the second switch, the first inputs of the fourth, fifth, and sixth elements AND, the output of the third element OR is connected to the second input of the first .I element, the first inputs of the counter, the first and second triggers, the second input of the sixth element This AND and the first input of the fourth OR element, the first output of the first decoder is connected to the second input of the second trigger and the second input of the counter, the outputs of which are connected to the inputs of the second decoder, the output of which is connected to the second input of the first trigger, the first output of the first trigger is connected to the first input of the third trigger and the second inputs of the second and fourth elements And the output of the fourth element And connected to the second input of the fourth element OR, the output of which is connected to the first input of the fourth trigger, the output of which The second output of the first trigger is connected to the second input of the fifth element, And the output of the second trigger is connected to the third input of the fifth element I. The output of which is connected to the second input of the fourth trigger, the output of the sixth element And is connected to the second input the third trigger, the output of which is connected to the third input of the first element AND, the second and third outputs of the first decoder are connected to the corresponding inputs of the OR-NOT element, the output of which is connected by the fourth input of the first element and AND, whose output is connected to the second vhotsom first register. Figure 1 shows the functional diagram of the device for inputting information; figure 2 is an example of the technical implementation of the first register; in FIG. 3, the connection of the inputs of the second element with the outputs of the encoder and the accelerator unit. The device contains a reading unit 1, an amplifier unit 2, the first 3, the second 4, the third 5, and the fourth 6 OR elements, the first register 7, the second register 8, the first silencer 9, the second switch 10, the memory block 11, the first pulse shaper 12 (on the leading edge), second pulse shaper 13 (on the falling edge), first 14, tbroy 5, third 16 fourth 17 and fifth fifth delay elements, first 19, second 20, third 21, fourth 22, fifth 23 and dough 24 elements And, the first 25, the second 26, the third 27 and the fourth 28 triggers, the first decoder 29, the score is 30, the second is decoded 31, encoder 32, ISH-NO element 33. The register 7 (2) has two inputs of fault. The first fault input is common, connected to the output of delay element 1, and zeroed all bits of the register. The second additional input input is connected to output I 19 and only zeroed the third register bit, the unit value of which in the MTC-2 corresponds to the SPACE character. The encoder 32 forms the SPACE code in MTK-2, containing a single value in the third code section and in the synchronization bit, and can be made in the jumper on the corresponding inputs of the element OR 4 (Fig. 3). The device works in the following way. The input information is otperforated on the tape line by line, for example. . (. UL., "A m 1" 4.GR. V BJAi.b. In the three-register code of the MTK-2, which contains three groups of characters, and three register signs - RUSSIAN, LATINSKY, FIGURES. The incoming message consists of consecutive from each line of a tape of parallel codes of register attributes and symbols, the codes of register signs immediately following the codes of each corresponding group of characters or codes of single characters. Each code contains six bits - five bit information and one sync bit, with this code register new sign RUScm coincides with the code missing

formations and has the following form: the value of the five information bits is logical 0, the value of the sync bit is logical 1 In the process of moving the carrier, the line coding signals are read by block 1 and then the amplifiers 2 are fed to the inputs of the OR 3-5 elements and the decoder 29. Through the OR 4 element, the read code is written to the register 8. The OR 3 element records the presence of a logical one. in any of the six bits of the code, since it detects an arrival in 1

When the register code of the RUSSIAN code arrives in the device, followed by the code of the corresponding character, the Russian register code is decoded at the first output of the decoder 29, the Pulse from the first input of the last is entered into the counter 30 and sets the trigger 26 to one.

It is prepared for opening by potential signals from the direct output of trigger 26 and the inverse output: trigger 25. When interrogating the AND 23 5 element, the input information device — the character codes and their register features. The element OR 5 analyzes I only five information bits of the input code and records the presence of at least one logical data in it. It detects the arrival of any character into the device, as well as LATIN and FIGURE per gistrrvyh signs, except for the register sign RUSW. SKY. The decoder 2 analyzes the incoming codes and detects the arrival of only the codes of the register features RUSSIAN, LATINSKY, FIGURE. The potential signal from the output of the element OR 3 is fed to the inputs of the formers 12 and 13 pulses along the leading and trailing edges. Impulse driver 12 through delay elements 14 and 15 and element 21 prepared to open the potentials from the inverse output of trigger 28, provides rewriting of information from register 7 through switch 9 into memory block 1, and through element 16 of delay delay the reset of register 7. Besides In addition, the pulse is formed by 1l 12 through the element 14 of the request {interrogates the element I 19 and -R the element 5. delay is the element And 20. The pulse from the output of the former 13 through the delay element 17 rewrites the contents of register 8 through the co fr y to 10 and the register 7 , and through the element 18, the delay then zeroes the register 8. In addition, the pulse of the former 13, through the delay element 17, polls the AND 22-24 elements. Thus, each input code is written to register 8, then the leading edge overwrites the previous code from register 7 to memory block 11, after which the falling edge is rewritten from register 8 to register 7, followed by clearing register 8.

The impulse from the output of the mapper) 3 through the delay element 17 - the element I 23 opens and the signal from its code sets the trigger, 28 to the one state, which closes the element 21 and blocks the rewriting of the code from the register 7 into the memory block. Upon receipt of the register sign code RUSSIAN, the elements of School No. 5 and I 19 are closed. By the arrival of the promising code, with the next line of the carrier in register 7, the code of the register feature RUSSIAN is recorded. Following the register sign code RUSSIAN the character code through the element OR 5 has wrapped the counter 30, triggers 2 and 26, and through the OR element b trigger 28, which again prepares {gives the element AND 2 to -opening. In this case, the pulse of the leading edge of the character code through the elements 14 and 15 of the set and the element 21 translates the code of the register characteristic RUSSIAN from register 7 into memory block II. The delay time of the elements 15 and 14 ensures the supply of a pulse to the input of the element I 2 after resetting the triggers 25.26 and 28.

When entering into a device of a group of codes of a register characteristic RUSSIAN, corresponding to the separation section between texts, the first code in the group is processed similarly to that described. In this case, as indicated, the trigger 26 is set to one state and the element AND 21 is closed. By the arrival of the subsequent second code RUSSIAN in register 7, the code of the first register characteristic RUSSIAN is written, which is not rewritten from register 7 to the AND block of memory by the leading edge of the second code . The second code of the register characteristic RUSSIAN and the subsequent identical codes of the separation section do not open the element OR 5 n the reset of the counter 30 and the trigger 28 does not occur. In this case, a regular pulse is recorded in counter 30, the state of counter 30 is decoded by decoder 31, and when the contents of the counter correspond to the state taken as a sign of the beginning of the separation section (for example, the number of RUSSIAN codes is 2) the output of the decoder 31 generates one; No state trigger 25. Last

prepares elements 20 and 22 for opening, closes element I23, and sets trigger one for one. In this case, the pulse from the output of shaper 12i formed on the leading edge of the second RUSSIAN code and delayed by elements 14 and 15 at the time of installation of the flip-flops 25 and 27 into a single the state enters through the element AND 20 to the input of the encoder 32, which forms the SPACE character code containing the logical 1 in the third bit and the synchronization bit and is written to the register 8 through the element OR 4. Then the pulse from the output of the former 1 formed on the falling edge of the second RUSSIAN code, through the delay element 17 and the switch 10 rewrites the SPACE code from register 8 into register 7 with the subsequent register 8 reset, and through elements AND 22 and OR 6 zeroes the trigger 28. I thus prepares to open element I 2I. The next, third 4SOD RUSSIAN, with the impulse of its leading edge, rewrites the SPACE code from register 7 into memory block 1 with register by resetting element 21 and switch 9, and through element | AND 20, encoder 32 and element OR 4 again, the SPACE code is written into the register 8. A trailing edge of the third code is RUSSIAN the SPACE code is rewritten from register 8 to the register 7 with the subsequent reset of the register 8. When the following register codes are received, the device works in a similar way. For each RUSSIAN code, a SPACE character code is generated, which is written into memory block 1I.

The end of the separation is determined by spruce. blowing way.

Each text, including the following one, always starts with a register sign - pycGKfTM, Latin or digital. In this case, the last line of the RUSSIAN code in the separation section is interpreted as the register code of the RUSSIAN only if the following first code of the following text is not a Latin or digital register code (d. The register code must be transmitted to If the first code of the next message is a Latin or digital register code, the RUSSIAN code in front of it in the separation section is not a sign of the Russian register and must be converted to the SPECIMEN code. L. When the first code of the following text is received, a signal appears at the output of the element OR 5, and the decoder 29 analyzes it to detect the Latin or digital register. In register 7, the SPACE character code generated from the previous RUS code is found. - SQUISITE DIVISION SECTION. The signal from the output of the element OR 5 zeroes the trigger 25, 26 and 28, the counter 30 closes the elements AND 20 and 22, which eliminates the formation of the SPACE character code, if the input code is not Latin or digital. register on the corresponding the second or third output of the decoder 29 does not generate a signal, the OR-NOT 33 element is open and outputs a signal to the AND 19 element, to the other inputs of which the signals from the outputs of the OR 5 element and the trigger 27 are also transmitted. The leading edge of the incoming first code the text is fed from the output of shaper 12 through element 14 to the input of element I 19. The delay time of element 14 is longer than the analysis time of the decryptor code 29. Element 19 opens and the pulse from its output suppresses the third digit of the SPACE code recorded in register 7. P and in that after it ustanayyivaets registrovog RUSSIAN feature code which is supplied in the manner described in the memory unit 1I. If the first code of the next message is a Latin or digital register, a signal is generated on the corresponding side of the decider 29 that closes the OR-NOT 33 and AND 19 elements. At the same time, the SPACE code remains in register 7, which then goes to block 11 memory The pulse of the falling edge of the first code of the next message is fed from the output of the imaging unit 13 through the delay element 17 to the element 24 which is prepared for opening by the signal from the output of the element OR 5. At the same time the element 24 also opens and the signal from its output zeroes the trigger 27. The device returns to the position corresponding to the transmission of text codes, and the described process is repeated. The proposed device provides continuous input of texts in multi-register codes plotted line by line on one carrier, divided between specific sections that do not carry useful information and contain codes with a single value of the synchronization bit, the formation of SPACE character codes corresponding to the separation sections between the texts, and their transfer to a memory block, which is achieved by introducing into it a register, a switch, an encoder, two decoders, a counter, three triggers, an OR-NOT element, four OR elements, five And elements and five delay elements. This allows you to enter texts continuously, without stopping them in the separation areas, as is done in known devices, allows you to visually separate the entered texts from each other after they are decrypted and displayed, for example, on the indicator screen or in the recording device, which eliminates correct reading of the information received, and thereby increases the accuracy and reliability of entering information in multi-register codes. Technical and economic efficiency in the use of the invention is determined by the increase in speed due to continuous input and expansion of the functionality and application area due to the possibility of entering information in multi-register codes.

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Claims (1)

DEVICE FOR INFORMATION INPUT, containing a reading unit, the outputs of which are connected to the inputs of the amplifier block, the outputs of which are connected to the inputs of the first OR element, the first register, the outputs of which are connected to the inputs of the group of the first switch, the outputs of which are the outputs of the device, the first and second pulse shapers, . the first element And, the first trigger, characterized in that, in order to increase the speed and accuracy of the device, a second register, a second switch, an encoder, first and second decoders, a counter, a second, third and fourth triggers, an OR-HE element, are introduced into it the second, third and fourth OR elements, the second, third, fourth, fifth and sixth AND elements, the first, second, third, fourth and fifth delay elements, the outputs of the amplifier block are connected to the inputs of the first decoder, the inputs of the first group of the second OR element and the inputs third ele IL, the outputs of the second OR element are connected to the inputs of the second register group, the outputs of which are connected to the inputs of the second switch group, the outputs of which are connected to the inputs of the first register group, the output of the first OR element is connected to the inputs of the first and second pulse shaper, the output of the first pulse shaper is connected with the input of the first delay element, the output of which is connected to the first input of the first And element and the input of the second delay element, the output of which is connected to the input of the third delay element and with the first inputs of the second and third AND elements, the output of the third AND element is connected to the input of the first switch, the output of the second AND element is connected to the input of the encoder, the outputs of which are connected to the inputs of the second group of the second OR element, the output of the third delay element is connected to the first input of the first register, the output the second pulse former is connected to the input of the fourth delay element, the output of which is connected to the input of the fifth delay element, the input of the second switch, the first inputs of the fourth, fifth and sixth elements in AND, the output of the third OR element is connected to the second input of the first AND element, the first inputs of the counter, the first and second triggers, the second input of the sixth AND element and the first input of the fourth OR element, the first output of the first decoder is connected to the second input of the second trigger and the second counter input the outputs of which are connected to the inputs of the second decoder, the output of which is connected to the second input of the first trigger, the first output of the first trigger is connected to the first input of the third trigger and the second inputs. SU .... 1157545 dams of the second and fourth elements AND the output of the fourth element And is connected to the second input of the fourth element of the PLI, the output of which is connected to the first input of the fourth trigger, the output of which is connected to the second input of the third element And, the second output of the first trigger is connected to the second the input of the fifth element And, the output of the second trigger is connected to the third input of the fifth element And, the output of which is connected to the second input of the fourth trigger, the output of the sixth element And is connected to the second input of the third trigger, the output of which is connected to the third input of the first AND gate, second and third outputs of the first decoder connected to the respective inputs of the OR-HE, whose output is connected to a fourth input of said first AND gate, the output of which is connected to the input of the first register vtorm.