SU1483449A1 - Number sorting unit - Google Patents

Abstract

The device relates to automation and computing and allows the selection from the input group of numbers those formats of which are within the specified limits. The purpose of the invention is to expand the functionality of the device by introducing a variable range of acceptable formats of sorted numbers - achieved by introducing new elements and new links between them. The device contains N - bit shift register 1, triggers 2, 3, 5, elements AND 4, 6, 7, four-bit shift register 8, elements OR 9, 10, prohibition elements 11, pulse shaper 12. The device determines whether whether the number arriving with a sequential code is in a predetermined range, pre-written in shift register 1 and triggers 2, 3. 1 Il.

Description

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The device relates to automation and computing and allows the selection of the input group of coded messages, the formats of which are within the specified limits.

The purpose of the invention is to expand the scope by introducing a variable range of acceptable formats of sorted numbers.

The drawing shows a diagram of the proposed device.

The device contains an n-bit shift register 1, triggers 2 and 3, which are additional bits of the shift register 1, element 4, trigger 5, elements 6, 7, four-bit shift register 8, element 9 9, element 10 , prohibition element 11, pulse shaper 12, information input 13, clock input 14, input 15 for recording boundaries of formats of sorted numbers, input 16 for the end of message indication, information output 17, output 18 for the tracking signal.

The device works as follows.

Before the arrival of the next number, the trigger -5 is set to O, and the combination 1000 is written to the four-bit shift register 8 (not shown). Then, to the installation inputs of the shift register 1 and the flip-flops 2 and 3, a combination is supplied to the input 15 of the device record, which defines the limits of the range of acceptable formats of the sorted number.

The structure of the combination is as follows: units are recorded in the first (leftmost in the drawing) i-th and j-th bits.

i n + 3-K;

j-rn-2-l, where K and 1 are respectively lower and

the upper limit of the range of acceptable formats of the sorted number.

The unit in the first position will be the right limit number entered in the device.

The coded message arrives at information input 13 by a serial code and, through the element SHSh 9, is recorded in register 1, the information is shifted in, which, as well as in triggers 2 and 3, is performed by clock pulses from input 14. In this case, the information on output 17 of the device not taken into account

since element 4 is closed and there is no tracking signal at output 18.

The information from the output of the trigger 3 through the open element And the prohibition enters the input of the shift of the register 8. If upon receipt of a sign of the end of the message to the input 16, the register 8 is in the state 0100, this indicates that the format of the sorted number is in the specified range. In this case, the pulse of the sign of the end of the message through the open element And 7 sets the trigger 5 to one state. At the time of the flip-flop of trigger 5, the pulse shaper 12 is triggered and a unit is added to register 1, which is the left limiter of the number entered in the device. "

Information from the output of trigger 3 continues to flow to the input of register shift 8 until it is in the state 0001 (which corresponds to the arrival at the input of register 8 of the right limit number), at which the element And 6 is opened, and the unit level from the trigger output 5 closes prohibition element 11, which blocks the change of state of register 8. At the same time, from the output of element 4, device 18 outputs a single level signal accompanying the sorted number output from output 17, the format of which is given range. The end of the issuance of the number occurs after writing in the trigger 3 of the left limit number. In this case, the register 1 and the trigger 2 are in the zero state and at the output of the SHSh 10 element a zero level is set, according to which the tracking signal is output from the output 18 of the device.

If, upon arrival at the device input, the sign of the end of the message, register 8 is in a state other than 0100, this means that the format of the sorted number is outside the specified range. In this case, the end of message impulse will not pass through the AND 7 element and the trigger 5 will remain in the zero state. The maintenance signal at the output 18 is not in accordance with one.

When sorting subsequent numbers, the device works in the same way.

Claims (1)

Invention Formula A device for sorting numbers containing a shift register, two flip-flops, an And element, a prohibition element, the shift register output being connected to the information input of the first flip-flop, the direct output of which is connected to the information input of the second flip-flop, the synchronization inputs of the shift register, the first and second triggers are combined, distinguished by the fact that, in order to expand the scope of application by introducing the inputs of the first and second triggers, the outputs of the bits of the shift register and the first trigger are connected respectively to the inputs of the second OR element, the output of which is connected to the first input of the first element AND whose output is the output of the device tracking signal, and the second input is connected to the output of the second element And with the prohibition input of the prohibition element, the information input of which is connected to the direct output of the second trigger and is information This prohibition is connected to the shift input of a four-bit shift register, the output of the second and fourth bits of which are connected respectively variable range of permissible for- jg device output, output of elements of sorted numbers, a four-bit shift register, a third trigger, two OR elements, a second and a third AND elements, a pulse shaper, and an information input with the first inputs second The third And elements, the second input of the third element And is the input of the sign of the end of the device message, and the output is connected to the installation output of which the input is a clock input 25 to the one state of the third trigger device, the inputs for writing the boundaries of the formatter, whose direct output is connected Comrades of the sorted numbers of the device under the second input of the second element K are connected to the installation inputs of the shift and, through the pulse shaper, with the first register and the second information — the second input of the first element OR. the input of the device is connected to the first input of the first OR element, the output of which is connected to the information input of the shift of the shift register, the inhibit synchronization is connected to the input of the shift of the four-bit shift register, the output of the second and fourth bits of which are connected respectively output of the device, the output is elementary with the first inputs of the second