SU1265773A1 - Multichannel priority device - Google Patents

Abstract

The invention relates to computing and can be used in computing systems. The aim of the invention is to expand the scope of use due to the possibility of working with the same priority codes in different channels. The device contains an encoder, and in each channel - a register, a decoder, an OR element, and in each channel, except the first, element I. A new element in the device is the introduction of an OR element, a group of K IS elements (, n is the number of channels), (n -) ptors, and into the channel there are groups of K elements And their connections in the device, which ensures the achievement of the objective of the invention. Gil.

Description

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00 The invention relates to computing and can be used in computing systems. The aim of the invention is to expand the scope of use due to the possibility of working with the same priority codes in different channels. The drawing shows a functional diagram of the proposed device. The device contains channels 1, element OR 2, group of elements OR 3, and in each channel 1, except the first, element AND 4, register 5, decoder 6, encoder 7, element IL 8, group of elements AND 9, group of request inputs 10, code input group 11, clock input 12, output group 13 and signal output .14. The device works as follows. The initial state of the device is characterized by the fact that, by the code inputs 11, non-left binary priority codes are recorded in registers 5. The highest priority corresponds to the lowest priority code value equal to one, the lowest priority is the code of the number n (n is the number of channels). Thus, priority codes, differing by a unit of the lower order, determine the order of servicing subscribers. In the presence of interrogation signals arriving at the inputs 10, decryption of the priority codes by the decoders 6 in the appropriate channels is allowed. The output signals of the decoder 6 are fed to the inputs of the encoder 7 of channel 1 so that for each encoder 7 signals from the same name of the decoder 6 of all channels are received. Let, for example, on all inputs 10 there be single signals, the nth subscriber is given the maximum priority. In this case, in the decoder of the 6th channel, the 1st output is excited, and at the inputs of the encoder 7 of the first channel,

unitary code 0 ... 01 is forced. At the output of the encoder 7 of the first channel, the binary code of the number of the nth subscriber is generated, which arrives at the first inputs of the And 9 elements of the first channel.

A single signal from the direct output of the element OR 8 through the element OR 2 is fed to the output 14 of the device, and a zero signal from the inverse output of the element OR 8 blocks the operation of the elements AND 4.

Claims (1)

home channel outputs of the encoders are connected to the inputs of the element OR of its channel, each output of the channel encoder is connected to the first input of the element of the same name AND the channel of its channel, the second inputs of which in each channel except the first are connected to the output of the element AND its channel in the first channel the direct output of the element OR is connected to the second inputs of the elements AND of the channel group, the third inputs of the elements32 The signal from output 1.4 used in the computer as a signal of the device’s readiness allows the interrogation signal coming in from the computer such as are for entry device 12. This signal transmits the binary code of the subscriber number from the outputs of the encoder 7 through the open elements AND 9 and the elements OR 3 to the outputs 13 of the device. 1Chapter 7 is a priority, therefore, if there are identical codes in registers 5 of several channels, the service of such devices is made depending on the location of this channel in the device. Multi-channel priority device containing a register, a decoder, an OR element in each channel, except for the first channel, an AND element, the channel register output is connected to its channel decoder input, the channel register input is a corresponding device code input, each request the input of which is connected to the control input of the decoder of the channel of the same name, the direct outputs of the elements OR of channels, except the first, are connected to the first inputs of the elements AND of their channels, the inverse outputs of the elements LI channels - to the corresponding inputs of elements AND subsequent channels, characterized in that, in order to expand its scope due to the possibility of working with the same priority codes in different channels, the element OR, the group of elements OR, are entered into it, and the encoder is entered into each channel, group of elements I, B1s1x: odes of elements OR groups are a group of device outputs, the 1st (, ..., n, n is the number of channels) the outputs of the channel decoders are connected to the inputs of the i-ro channel encoder, in each 12657734. Commands and groups of all channels are connected to the corresponding channel, the output element of the clock input of the device, direct OR is the signal output the output of the element OR of the first as-a-device, the outputs of the same name electro-connected to the first input of the elements And groups of channels are connected to OR, each subsequent entrance to which; the inputs of the elements of the same name OR go connected to the output of the element And the co-group. but, 1Ш