SU1107133A1 - Device for computing coefficients of walsh-adamard transform - Google Patents

Abstract

A DEVICE FOR CALCULATING TRANSFORMATION COEFFICIENTS BY WALSH-ADAMARA, containing 2 correction registers, a group of OR elements, 2 switches and 2 adders, characterized in that, in order to improve performance, a mode trigger, first and second groups of result registers, and a second and second group of result registers and a group of result registers and a group of result registers and the second and second groups of result registers and the second and second groups of result registers and the second and second groups of result registers and the group of result registers and multibore code in dvuhradny, each of which contains K groups of M subgroups of adders of the same weight j

Description

The invention relates to radio engineering, in particular to spectral analysis, and can be used in digital signal processing in radio, hydro, and sonar, in navigation, communications, telemetry, and other technical equipment. A device for calculating Walsh transform coefficients is known, comprising (N-transform dimension) stages of a single transform, each of the stages contains a shift register, an adder and a subtractor, a group of elements And a control unit t11. The disadvantage of this device is the low speed due to the sequential method of calculating the coefficients. It is also known a device for converting to Walsh functions, containing a shift register, totalizer-calculators, adders, information signal switch, active pulse switch, Walsh function generating unit - Reader, where the information inputs of the adders are combined and are the device input, the control inputs of the adders are connected to the outputs of the corresponding register bits shift, and the output sum is connected to the inputs of the information signal switch, the control inputs of which are connected to the outputs of the Rademacher functions of the Walsh-Rademacher function block, and the output of the information signals switch are connected to the information inputs of the adders-subtractors, the control inputs of which are connected to the codes of the corresponding functions Walsh-Walsh-Rademacher function block, the input of the clock switch is the clock input of the device, the first and second outputs of the switch are clock the output pulses are connected to the clock inputs of the shift register and the Walsh-Rademacher function block, respectively, the control input of the clock switch is connected to the overflow output of the shift register C 21. The disadvantage of this device is the low speed due to the sequential reading of accumulated values from the adders to the adders feeders and time costs for the accumulation of the sums of the ordinates of the investigated process in adders. The closest technical solution to the invention is an orthogonal digital signal transducer according to Walsh-Hadamard, containing 2 adders (L-order of conversion), 2 registers, 2 blocks of OR elements, 2 blocks of AND elements, and a block of forming time intervals, and The information input of the device (,.,., 2) is connected to the information at the input of the (2g-1) -th 6 blocks of I elements, the output of the i-th adder is connected to the information input of the 2-nd block of I elements, and the control inputs of the blocks of I elements with numbers () and 2i connected with Respectively to the direct and inverse outputs of the block of formation of time intervals, the outputs of the (2r-1) -th and 21th blocks of the elements AND through the t-th block of elements OR connected to the input of the i-ro register, the outputs of the () -th and 2i -ro registers (j 1, ..., are connected to the inputs of the i-th and (d + + 2) -th adders-subtractors, the outputs of the registers are the outputs of the C31 device. The disadvantage of the known device is its low speed. The purpose of the invention is to increase the speed of the device. . The goal is achieved in that a device containing 2 correction registers, a group of elements OR, 2 switches and 2 adders are entered into a trigger of the mode, the first and second groups of result registers and a group of converters of a multi-channel code into two-dny, each of which contains K groups from M subgroups of adders of the same weight 3 (is the number of the discharge), with the information outputs of the adders of the d-th subgroup (, M) of the i-th (, K-1) group respectively connected to the inputs of the adders of the i-th subgroup (% + 1) th group, transfer outputs adders Groups of the i-th group are respectively connected to the inputs of the adders of the -th (, (C) subgroup of the (t + +1) -th group, inputs of the adders of the first group of the i-th (i 1,2) converter of the normal code to the two-row one are combined with the information output of the i-ro registrar register is the i-th information input of the device.

information codes of adders of the K-th group of the r-th (, 2) converter of a multi-channel code into a two-row one, respectively, are connected to the inputs of the i-ro switch, the first output of which is connected to the input of the 1st adder, the output of which is connected to the first input ii-ro of the OR group, the output of which is connected to the information input of the Vth result register of the first group, the direct and inverse outputs of the mode trigger are connected respectively to the first and second control inputs of the i-th switch (, 2), the output of which is connected to the second input ъ th ale coagulant OR group and information input i-ro second group result register, inputs of flip-flop D and 1 are respectively the first and second mounting device inputs.

Fig. 1 shows a functional diagram of an apparatus for calculating conversion factors according to Vonmy Hadamard in Fig. 2, a diagram of a multi-code converter; in FIG. 3, the process of converting a multi-code to a two-bit in the case of building a multi-code converter in three-input single-bit totalors for the order of the conversion of h 3 and bit operand 8.

The device (Fig. 1) contains paraphase information inputs with buses 1 and 2, respectively, of direct and reverse codes, converters 3 of a multi-code code into a two-row one with input buses 4 of a multi-code and output buses 5 of a two-code code, a group of correction registers 6, switches 7, trigger 8 modes with tires 9 and 10 of the trigger setup, respectively, in single and zero states, a block of registers 11 consisting of two groups of result registers 12, a group of elements IL 13 and adders 14.

Each converter 3 of a multi code into a two-channel code (FIG. 2) contains groups of adders 15 consisting of

from subgroups of adders 16, which combine i-entry single-bit adders 17 of the same weight. Each switch 7 (figure 1) contains two groups of elements And 18.

The device works as follows.

The Paraphase information inputs of the device from the direct and inverse outputs of memory registers (not shown) simultaneously receive 2 samples of the signal. In accordance with the values of the Walsh functions of the Hadamard function (for example, for P 4, the values of the Walsh functions are given in the table) each of the signal samples in the forward or reverse code goes to the bus group 4 of the multi code of each of the transducers 3 codes. Thus, a combination of signal counts + XO, + X1, -X2, -X3, + X4, + X5, -X6, + X8, -X10, -X11, + X12 is fed to the input of the fifth code converter via the tires of a multi-code; + X13, -X14, -X15 (see table). On the other tire group of the multi code, the correction code is received. Correction codes (for each of the converters 3 of the multi code) are recorded in advance in groups of correction registers 6 and correspond to the number of signal samples involved with a negative sign in the formation of a given conversion factor.

Correction codes are needed to obtain negative signal samples not in the return code, which is the case on tires 2 in the return code, but in additional codes, as is necessary for organizing the computation process. To translate a negative number from the return code to an additional correction, it is sufficient to add one to the low order of the return code of each negative number. To reduce the time spent on the specified translation of the inverse codes of negative numbers into additional codes, correction codes are formed in advance and written into the corresponding correction registers. The ny are binary position codes of the number of samples fed to the input of the corresponding converter 3 codes with a negative sign. For example, when converting p 4, the correction code for the fifth code converter is 8, since the number of signal samples that take part in generating a conversion coefficient with a negative sign is 8 (see table for a value). Therefore, in the fifth register of the correction register group, the binary code 1000 will be pre-recorded. The resulting multi-port code, delivered via the multi-code code 4 bus to the code converter 3, is converted into a two-digit code. The process of this conversion is illustrated in the case of .P. 3, fi 3,, and in FIG. 3 (each point represents the binary digit of the weight). The numbers of the same weight are located one below the other and are fed to the adders of the same group. Adders belonging to the same group begin to work at the same time point. The dotted line circled correction code. Each frame in FIG. 3 selects the numbers supplied to the input of one adder. At the output of each three-input adder, a digit of the sum of the same weight and a jiepeHoca digit of the neighboring greater weight are formed. Source Matrix .A, Corresponding

multidot code, sequentially converted into a two-row code. The generated two-row codes are supplied to the corresponding switches controlled by the mode trigger 8, and depending on the preset mode (determined by the presence of a logical unit on one of the input buses 9, 10 of the mode trigger) are immediately written to the result register groups 11 or converted to one dna codes on adders 14.

Thus, organizing parallel computation of conversion factors per unit cycle of operation of the device and presenting the results with one or two codes significantly improves the device speed, which allows the proposed device to be used in building digital signal processing devices operating under tight time constraints.

1

Fi9.2

8 7 6 S 4 3 g 1 Np

Fig.Z

Claims (1)

DEVICE FOR CALCULATING TRANSFORMATION COEFFICIENTS BY WALSH-ADAMAR, containing 2 ^P correction registers, a group of OR elements, 2 ^P switches and 2 ^P adders, characterized in that, in order to improve performance, a mode trigger, the first and second groups of result registers are introduced into it and a group of converters of a multi-row code into two-row code, each of which contains K groups of M subgroups of adders of the same weight j (j-digit number), and the information outputs of the adders of the jth subgroup (j = 1, M) 't ((= 1, K-1) groups, respectively are connected to the inputs of the adders of the jth subgroup of the (b + 1) -th group, the transfer outputs of the adders of the j-th subgroup of the L-group are respectively connected to the inputs of the adders of the tn-th (ni = j + 1) subgroup (1 + 1) - of the ith group, inputs of the adders of the first group of the ith (gm ₍ 2 ⁿ ) multi-row code to two-row code converter are combined with the information output of the i-ro correction register and is the ith information input, devices, information outputs of the adders of the Kth group i-ro (€ = 1.2 °) multi-line code to two-line code converters are respectively connected to the inputs of the i-ro switch I, whose first output is connected to the input of the t-th adder, § whose output is connected to the first input of the ith element OR of the group, the output of which is connected to the information input of the i-ro register of the result of the first group, the direct and inverse outputs of the mode trigger are connected respectively to the first and second control inputs of the t-ro switch (b — 1,2 *?, whose output is connected to the second input of the ith element of the OR group and the information input of the ith register of the result of the second group, the setting inputs 0 and 1 of the mode trigger are respectively first and the second installation inputs of the device. SU _t . 1107133 1 1107133