SU1541602A1 - Device for computing vector modulus - Google Patents

Abstract

The invention relates to the field of computing and can be applied in digital signal processing equipment with quadrature components for calculating a signal module in real time. The aim of the invention is to increase speed. The device contains the first 1 and second 2 comparison circuits, the first 3 and second 4 switches, the first 6 and second 7 registers, the block 5 of switching the arguments of the multi-code, the block 8 of the multi-code conversion, the adder 9, the inputs of the first 10 and the second 11 arguments, output 12 results. 2 hp f-ly, 4 ill.

Description

eight

-V

12

The invention relates to computing and can be used in specialized computers,

The purpose of the invention is to increase speed.

FIG. 1 shows the functional scheme of the device; in fig. 2 is a block diagram of the switching unit of the arguments of the multi code; in fig. 3 is an example of implementation of a multi-code conversion unit for n (n is the width of the argument); 4 shows the process of converting a multi-code.

1 The device contains the first 1 and second 2 comparison circuits, the first 3 and second 4 switches, the first 6 and second 7 registers, the block 5 of switching the arguments of the multi-code, the block 8 of converting the multi-code, the adder 9, the inputs of the first 10 and the second

, 11 arguments and output 12 results.

i The switching unit of the arguments of a multi-code contains an element NK 13, - elements ШШ 14,145, respectively, from first to fifth, groups of elements And 15, -15, respectively, from first to fourth, each of which contains elements 16, -16 group of elements NAND 17, consisting of NAND 18 elements, l 8n.

- Multiple code converter contains adders 1 У4 -1 92fh,) of the first group, adders 20, -20P4. Of the second group and adders 21, -21niM - the third group.

 The device operates as follows.

The device implements an approximation algorithm.

 4 + 3si / 16 2S, - ;;

 3L, / 4 + 11 Si / 16, 2S, L {; where (1C (L, I Y, - 1), (l X-l,

| a, -l).

The inputs of arguments 10 and 11 and the inputs of switches 3 and 4 receive n-bit codes of value I X | and IY). Comparison circuit 1 generates signal 1 at | X or O at jXU / Yl, arriving at the control input of switches 3 and 4. In the first case, registers 6 and 7 receive codes 1x1 and lY l, respectively.

L values; and C, - arrive respectively at the first and second inputs of the block 5 switching arguments a lot

five

0

5 Q

five

0

five

0

five

Row code. The comparison circuit 2 generates a signal 1 at L (or O when Lj, -. In the first case, the unit level signal from the control input of the argument switching unit 5 of the multi-channel code allows the passage of the ti code to the second and third outputs, and the L code (- on the fourth output of the block 5 switching the arguments of the multi code.

In the second case, the signal of the unit level from the output of the element NOT 13 allows the passage of the code S, - to the first, second and third outputs and the code LJ to the fourth and fifth outputs of the unit 5 for switching the arguments of the multi code.

The switching of the input bit lines of the converter of the multi-code 8. With the inputs of its adders ensures the formation of the multi-code code matrix consisting of the codes Sj / 8, / 16, L, and the inverse L- / 4 code.

FIG. 4 dots denote binary bits of codes of corresponding weight, circles — bits that take the value of the higher bit of the reverse code T-1, / 4, and the + sign indicates the correction code (QC) used to form the additional code from the reverse L (4 - the low-order unit of the L- / 4 code .. Frames surround the bits supplied to the inputs of the adders. The number of conversion steps is placed near the horizontal lines, the conversion time is also there: T5 is the tact of the single-digit adder; T (n +1) Tg is the clock of the parallel adder 9.

Claims (3)

1. A device for calculating a vector module comprising a first comparison circuit, two switches and an adder, the first argument input connected to the first operand input of the first comparison circuit and the first information input of the first and second switches, the second argument input connected to the input of the second operand of the first circuit comparison and with the second information inputs of the first and second switches, the control inputs to which are connected to the output of the comparison circuit, the output of the adder is the output of the device, characterized by m that, in order to increase speed, In addition, a multi-code argument switching unit, a multi-code conversion unit, a second comparison circuit and two registers are added, the outputs of the first and second switches are connected to the information inputs of the first and second registers, respectively, the output of the first register is connected to the input of the first operand of the second circuit the comparison and with the first information input of the switching unit of the arguments of the multid code, the output of the second register is connected to the input of the second operand of the second comparison scheme and with the second info The multi-code argument switching unit input, the control input of which is connected to the output of the second comparison circuit and the output of the multi-code code switching unit group is connected to the information inputs of the multi-source code conversion unit group, the first and second outputs of which are connected to the first and second outputs second term adder. i 2. The device according to claim. Characterized in that, in order to realize approximation coefficients equal to (1 and 3/16) and (3/4 and 11/16), the switching unit of the arguments of the multi-part code contains four groups of elements, And, a group of elements AND-NOT, five elements OR, element NOT, and the bits of the second information input of the block are connected to the first inputs of the corresponding elements AND groups from the first to the third, the second inputs of the elements AND groups from the first to the third are combined and connected to the outputs of the ISh1 elements, respectively from the first but the third order of the first information unit inputs are connected to the first inputs of the corresponding AND elements of the fourth group and with the first inputs of the corresponding AND-NOT group elements, the second inputs of the AND elements of the fourth group are combined and connected to the output of the fourth OR element, the second inputs of the AND-NOT elements are combined and connected to the fourth output element SH, the second inputs of the elements AND-NOT are combined and connected to the output of the fifth element 11) W, the first and second inputs of the first and fifth elements OR are combined and connected to the output of the element NO, whose input is İnönü to the first inputs of elements ten 20 25 . ,, 541602 SHSh from the second to the fourth and connected to the control input of the block, the second inputs of the OR elements from the second to the fourth are combined and connected to the output of the HE element, the outputs of the first and fourth elements of the AND to the first and fourth groups of the elements are connected to the outputs of the first by the fifth group. 3. The device according to claim. Characterized in that, in order to realize approximation coefficients equal to (1 and 3/14) and (3/4 and 5 11 / -4 6), the conversion unit of the multi-channel code contains the first group of adders from 2 (n-1) elements (n is the width of the arguments), the second group of adders from (n + 2) elements and the third group of adders from (n + 1) elements, and the bits from the first to (n-3) -th first the information input of the group is connected to the inputs of the first components of the adders of the first group from the third to (p-1), respectively, (p-2) -th (p-1) -th and n-th bits of the first information in the course of the group is connected to the inputs of the first terms respectively (2 (p-1) -2) -th, (2 (p-1) -1) -th and 2 (p-1) -th adders of the first group, bits with the first by (p-1) -and the second information input of the group are connected to the inputs of the first components of the first and second, respectively, and the inputs of the second component, respectively, of the third but (p-T) adder of the first group, n-th bit of the second information the group input is connected to the input of the first addend (n-1) -th adder of the second group, the bits from the second to the n-th third information input of the group are connected to the input The first and second second terms respectively and the third term inputs from the third to (n-1) -and adders of the first group, the bits from the first to (n-1) th fourth information input of the group are connected to the inputs of the first adders the first group, respectively, from the nth to (2 (p-1) - -3), and with the inputs of the second terms of the adders of the first group, respectively (2 (p-1) -2) -th to (2 (p-1) -1) d, p-and the bit of the fourth information input-group is connected to the input of the first addend (n + 2) -th adder of the second group, first and second time Row d p the information entry group thirty 40 45 50 connected to the inputs of the first terms of the first and second mators of the second group, respectively; bits from the third to the nth fifth information of the group are connected to the inputs of the second terms of the adders of the nth to (2 (pT) -3 ) -th of the first group and with the inputs of the third components of the adders, respectively (2 (p-1) -2) to (2 (p-1) -1) -th group of the first, the n-th digit of the information input of the group is connected to the input of the third term of the 2 (p-1) -th sum-torus of the first group and the input of the second spagahn (n + 2) -th adder of the second group The second summer of the first group is connected to the input of the correction code, the cjyMM outputs of the second and third adders of the first group are connected to the inputs of the second terms of the first and second adders of the second group, respectively, and the outputs of the summers of the fourth through (p-1) -th first group of with the inputs of the first adders respectively from the third to ( p-2) -th of the second group, the output amount (2 (p-1) 2) -th adder of the first corpse - connected to the input of the second addendum-mgo (p-1) of the second adder of the second group, outputs of the sums (2 (p-1) -1) -th and 2 (p - -1) adders of the first group are connected to the inputs of the first components of the nth and (n + 1) -th sum, respectively mators of the second group, the outputs of the first, second and (n-l) -ro sum Q 5 0 five mators of the first group are connected to the inputs of the third component of the first, second and (p-1) -th adders of the second group respectively, the carry outputs of the third to fourth adders of the third group are connected to the inputs of the second adders of the third and fourth groups of the second group, inputs third terms of which are connected to the outputs of transfers of adders, respectively, from the n-th to (n + 1) of the first group, the outputs of the transfers of adders from (2 (p-1) -2) -th to 2 (p-1) -th are connected to the inputs second terms adders, respectively, with the p-th p (n + 2) of the second group, the outputs of the sum of the adders of the second group from the second to (n + 2) -and connected to the inputs of the first components of the adders, respectively, from the first to (n + 1) -and the third group, the outputs of transfers of the adders of the second group at (n + 1) -th are connected to the inputs of the second terms of the corresponding adders of the third group of the same name, the carry outputs of the adders of the first group from the n-th to (2 (n-1) 3) -th are connected to the inputs of the third adders of the third to (p-2) -th of the third group, the outputs of the north-third adders of the third group from the second to (n + 2) -and transfer output (p + 2) -th adder of the second group is connected to the first output of the block, the second output of which is connected to the transfer outputs of all the adders of the third group. SN M t % 41 J . Z09lV l Si / 16 W + Y FIG. four - lilt Sill.KK Si / 8 -ito) g to) No.) -4 (b)