SU1262498A1 - Variable priority device - Google Patents

Abstract

The invention relates to automation and computing, and more specifically to priority devices, and is intended for use in specialized computing and control systems. The aim of the invention is to improve the speed of the device. The variable priority device contains the request register, the control code register, the first group of W elements AND (t is the number of subscriber priority sequences used), the OR element, the pulse generator, the control trigger, the synchronization trigger, the AND element, the ORINE element, the second group of n elements And (n is the maximum number of serviced subscribers), a group of n elements OR, and a group of w blocks of elements AND, each of which contains n elements I. The device provides parallel signal generation c and coding of used subscriber priority sequences, & as well as synchronization of the processes of receiving requests and finding the priority itself (Personal Request. 2 Il.

Description

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Claims (1)

00 The invention relates to automation and computing, and more specifically to priority devices, and is intended for use in specialized computing and control systems. The aim of the invention is to improve the speed of the device. FIG. 1 shows a block diagram of a variable priority device; in fig. 2 shows a table of correspondence between priority codes and subscriber priority orders. The device (Fig. 1) contains the priority register 1, the decoder 2, the query register 3, the element OR 4, the trigger 5, the group of elements AND 6, the trigger 7, the elements OR 8 of the group, the output elements AND 9 of the group, the element OR-NOT 10, pulse generator 11, element 12, device clock input 13, device code inputs 14, device request inputs 15, device start input 16, device signal output 17, device outputs 18. The device works as follows. The initial state of the device is characterized by the fact that trigger 7 is in the zero state and there is no signal at the input 16 of the device (zero signal level). Accordingly, the trigger 5 will be in the zero state (due to the unit with the inverse output of the trigger 7) and there will be no signals at the outputs 18 of the device (zero signal levels). The state of register 1, register 3, inputs 13-15 and output 17 of the device is arbitrary. Prior to the beginning of data exchange between subscribers and a digital computer, a priority code is recorded from the device inputs 14 to register 1 when the clock signal is applied to the device input 13. The control code is recorded by software programmer or by the operator’s console. The priority code determines the order of priority of subscribers. The correspondence between the priority codes and the order of subscriber priorities is presented in the table (Fig. 2). The operation of the device begins with a trigger signal sent to its input 1Q, which, if there is a signal at the output 17 of the device (indicating the presence of request signals that passed through the OR 4 element), goes through the AND 12 element to the trigger input of the trigger 7, translating it to the leading edge in unit state and permitting the installation of flip-flop 5 on the control input to which negative polarity pulses are received from the output of generator 11. To translate flip-flop 5 into single unit, the trailing edge of the pulse is used, creating conductive positive differential voltage on the control input flip-flop 5, as on the leading edge of the pulse register 3 requests receives requests from subscribers from the input 15 the device, and during the pulse duration at element outputs OR 8 group is set true information of highest priority requesting subscriber. It happens as follows. In accordance with the code value in register 1 at the corresponding output of the decoder 2 there will be a single signal unlocking And 6 elements of the corresponding block on the first inputs. The request signals from the outputs of register 3 are received at the second inputs of the corresponding elements of block B (in accordance with the positions occupied by subscribers in the priority sequence encoded by the code in register 1), while the highest priority request blocks all other requests, locking the corresponding elements of AND 6 block, and passes to the output of the corresponding element OR 8 groups. On the falling edge of the pulse from the output of the generator 11, a trigger 5 is set, the unit at its output unlocks the elements AND 9 of the group, and the signal formed at the output of one of the elements OR 8 of the group corresponding to the priority requesting subscriber itself goes to the corresponding information output 18 of the device, initiating information exchange between the digital computer and the corresponding subscriber. In this case, the subscriber removes his request, and the digital computer removes the polling signal. In addition, the signal from the output 18 of the device through the element OR-NOT 10 enters the reset input of trigger 7 and resets it, sets the trigger 5 to the zero state, which prohibits the issuance of signals to the information outputs 18 of the device and ensures a one-time operation of the device from single trigger signal. A new cycle of operation of the device begins with the filing at its input 16 of the next trigger signal generated by the digital computer after the exchange with the previous subscriber is completed. The transition from one priority sequence to another is carried out simply and quickly by writing a new control code to register 1. As in specialized computational and control systems, the number of operating modes and the corresponding priority sequences of subscribers usually do not exceed several tens, the register size 1 code will be no more than eight, and the change of operation modes (subscriber priority sequences) will be made during the execution of the output command DVR. The invention includes a variable priority device containing a request register, a priority register, m groups (m is the number of subscriber priority sequences), of n And elements, a group of n And output elements, and a decoder, the group of request inputs of the device connected to the group of information inputs of the request register The outputs of the output elements AND groups are the group of outputs of the device, the information inputs of the priority register are a group of code inputs of the device, characterized in that, in order to increase quickly action, it contains an OR element, a pulse generator, two flip-flops, an AND element, an OR-NOT element and a group of n OR elements, the clock input of the priority register is the clock input of the device, the outputs of the priority register are connected to the decoder inputs, each Jth the output of the decoder (jl, 2 ... m) is connected to the first inputs of elements And the j-th group, the direct output of each i-ro bit of the query register (1 2, ... n) is connected to the second input of the k-th element And j-groups (where k is the position number taken by the JM subscriber in the j-th priority sequence, in the maximum output of each 1st bit of the register of requests is connected to the corresponding inputs of all elements AND j-th group from (k + 1) -th to n-th, the output of each k-th element AND j-th group is connected to the JM input The i-ro of the OR element of the group (i is the number of the subscriber occupying the kth position in the j-th sequence of subscriber priorities), the output of each i-ro element of the OR group is connected to the first input of the i-ro output element of AND group, the second inputs of the output elements and groups are connected to the output of the first trigger, the clock input and the reset input of which are connected according to with the output of the pulse generator and with the output of the second trigger, the reset input of which is connected to the output of the element OR NOT, whose inputs are connected to the outputs of the device, the start input of which is connected to the first input of the element And, the output and second input of which are connected respectively to the installation input of the second a trigger, with a signal output of the device and with an output of an OR element, the inputs of which are connected to the direct outputs of the query register, the clock input of which is connected to the output of the pulse generator. / 4 H 15 15 15 sixteen FIG. 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