SU974393A1 - Data compressing device - Google Patents

Description

The invention relates to telemetry and can be used in various information transmission and processing systems. A device for compressing information is known, which contains a memory block, the first input of which is connected to the input of the device, the output of the memory block is connected to one of the inputs of the comparison unit, the first output of which is connected to the second input of the memory block, the output of the block of key elements is connected to the output devices, an arithmetic unit L. However, this device has a n CIM compression factor on linear or nearly linear sections. Closest to the proposed technical entity is a device for compressing information containing a memory block, the first input of which is connected to the input bus, the first output and the second input of the memory block are respectively connected to the first input and the first output of the first comparison unit, the second input of which connected to the control bus. aperture, function, the second output of the first comparison unit is connected to the input of the sign determining unit, the output of which is connected to the first input of the key element block, the output of which is connected to the output bus, the second comparison unit, the time interval comparison unit, the increment sign determination unit 2. However, the device has low accuracy in areas with accumulating changes and areas of tracking extremes. The aim of the invention is to improve the accuracy of information transfer. The goal is achieved by the fact that in a device for compressing information containing a memory unit, the first input of which is connected to the input bus, the first output and the second input of the memory unit are respectively connected with the first input and the first output of the first comparison unit, the second input of which is connected to the bus the aperture control function, the second output of the first comparison unit is connected to the input of the sign determining unit, the output of which is connected to the first input of the block of key elements, the output of which is connected to the output bus, and the second unit with The elements, the clock selection unit, the argument storage unit and the argument aperture unit, whose inputs are connected to the control bus for the argument argument and the first output of the argument storage unit, whose inputs are connected to the outputs of the clock selection unit, are entered. and the fourth inputs of the memory unit and with the output of the sign determining unit, with the first input of the element I, with the first output of the first comparison unit and with the first output of the second comparison unit, the second output of which and the second output of the memory block are This is connected to the fifth input of the memory unit and to the second input of the element I, the output of which, the second output of the memory unit, the third output of the second memory unit, the sixth input of the memory unit and one of the outputs of the clock extraction unit are connected to the second, third the fourth and fifth inputs of the key element block, the input of the clock pulse-selection block is connected to the input bus, the fourth input of the argument memory block is connected to the second input of the second cp & block, the third input of which is connected to the output of the argument aperture block.

FIG. 1 is a block diagram of the device; in fig. 2 and 3 are diagrams for the operation of the device.

The block diagram of the device includes an input bus 1, a block for selecting clock pulses 2, a block of memory 3, a block of comparison 4, a block of determining sign 5, a block of argument 6, an aperture block of argument 7, a block of comparison 8, element 9 block of key elements 10, output bus 11, function aperture control bus 12, argument aperture control bus 13. Process H-22 points illustrate

signal passing through different blocks (fig. 2 and 3).

The device works as follows.

The message data from the input bus 1 comes in the form of code words of the specified size by a serial or parallel code. The clock pulse allocation unit 2, comprising a device for allocating the first clock pulse and a device for selecting the clock pulses of words, produces, upon receipt of the first information word, the allocation of the first clock pulse and the formation of each clock pulse of words. The first clock pulse goes to the memory block 3 and the memory block of argument 6, sets all their registers to their initial state, and simultaneously to the block of key elements 10, where it opens the input key elements.

Claims (2)

The first information word (Fig. And 3, point 14) is written to one of the registers of block 3 via bus 1 by a clock pulse and transferred to block 10 by means of a delayed clock pulse and then through open key elements to the output bus 11. The same word is transmitted to block comparison function C. The next word goes to block 3, where it is also stored in the second register and simultaneously transmitted to the second register of block C. A comparison is made of the data difference of the two registers with the data in the aperture register installed over the control bus 12 Enjoy the aperture function. If the difference between words does not exceed the aperture, block k generates a signal using the reset pulse circuit, erasing the last word in the register of k and register of block 3. Then this process is repeated for each successive word until the next difference between the first and last in a word, it will not exceed the established aperture (Fig. 2 and 3, point 15). At the same time, clock pulses are counted, which arrive in the first register of the memory block of argument 6. When the set aperture is exceeded, block 4 uses a control circuit to generate a signal of a logical unit, which enters input element 9, which erases the first base word in block 3, stops the clock count pulses in the base word register and transfers the contents of the two block registers to the character definition block 5. The character definition block 5 compares the received data, determines the sign, and translates the sign data into tr storage places. At the same time, from block 6, the contents of the base word register (FIGS. 2 and 3, segment) are translated without destruction into the aperture block of argument 7. Then the process in blocks 2-6 proceeds similarly until the point 16 is determined (FIG. 2, FROM), after in block 5, the new data is compared (figures 2 and 3, points 15 and 16), the definition of the next character, the comparison of two characters and in the case of their identical names, the block 5 generates a signal to erase the penultimate character value, while the control signal on its no output. At this interval, the current word of the next register of block 6 is filled with the clock pulses. After that, a signal is generated that sends the contents of the two registers to the comparison block of argument 8 without erasing the data in block 6. The aperture block of argument 7 depends on the number of clock pulses set aperture on the aperture control bus of argument 13, determines the permissible absolute value of the aperture along the X axis and sends this data to the argument comparison block 8. The latter calculates No difference between the contents of the two registers of block 6 and compares this difference with the aperture value generated by block 7. If the difference does not exceed the aperture value, block 8 generates a signal at the output, erasing data from the second register of block 6. A similar process occurs for words between points 16 -17 I1 (Fig. 2 and 3). When the set aperture is exceeded along the X axis compared to the base word (Fig. 2, 18-19), block 8 generates a logical unit at the output, -which enters AND 9 and block 3 as a result, in t5lok, a signal is received that permits information word (Fig. 2. point 19), which comes from the register of block 3 to output 11. Simultaneously from block 8 In block 6, a signal is received, erasing the data of the base word (Fig. 2), and the word in the second register of block 6 ( Fig. 2, 18-19) becomes in turn basic for the following similar operations before transmissions. and points 7 (fig. 2). In the event that the symbol definition block 5, during the analysis, detects a change in the sign of the increments (FIG. 3, points 19, 20, 21), a signal is generated at its output that opens the key elements of the block 10 and. sends the last but one word from block 3 to output 11 (fig. 3, point 20). At the same time, the penultimate value of the character is erased, in block 6, the base word data (in this case J-TB in Fig. 3) is erased and the last segment (Fig. 3 | 20-21) becomes the base one. When processing signals of very low intensity, for example, a constant level for a long time, the memory block of the number of clock pulses 6 completely fills the registers, since the t and 5 blocks receive reset signals. In such situations, after the register is completely filled block 6, it is reset. At the same time, block 6 sends a signal to blocks 3 and 10 for the forced transmission of the information word to the output 11 of the device. Thus, the proposed device for compressing messages, as compared with the known ones, with equal compression factors and a signal processing aperture, allows an increase in transmission languor when passing through extreme message sections by an order of magnitude or more. An apparatus for compressing information comprising a memory unit whose first input is connected to the input bus, the first output and the second input of the memory unit are respectively connected to the first input and the first output of the first comparison unit, the second input of which is connected to the function aperture control bus , the second output of the first comparison unit is connected to the input of the sign determining unit, the output of which is connected to the first input of the key element block, the output of which is connected to the output bus, and the second comparison unit, different In order to increase accuracy, an element I, a block for selecting clock pulses, an argument memory block and an argument aperture block are inputted to the device, the inputs of which are connected to the argument aperture control bus and the first output of the argument memory block whose inputs connected to the outputs of the clock extraction unit, to the third and fourth inputs of the memory unit and to the output of the sign determining unit, to the first input of the And element, to the first output of the first comparison unit and to the first output of the second comparison unit, the second output cat The second and second outputs of the memory block of the argument are connected to the fifth input of the memory block and to the second input of the AND element whose output 38 is the second output of the memory block, the third output of the second memory block, the sixth input of the memory block and one of the outputs of the block selection of clock pulses are connected to the second, third, fourth, fifth inputs of the block of key elements, the input of the clock extraction unit is connected to the input bus, the fourth input of the argument memory block is connected to the second input of the second comparator, the third input of which is connected to the output of the argument aperture block. Sources of information taken into account in the examination 1. Manovtsev A.P. Fundamentals of the theory of radio telemetry. M., Energie, 1973, p. 33-438. 2. Author's certificate of the USSR № 729613, cl. G 08 C 15/06, 1979 (prototype),