SU840879A1 - Direct- to-supplementary code converter - Google Patents

Description

one

The invention relates to computing, serves to convert direct code to additional code and can be used in arithmetic and other digital information processing devices.

Known converters direct code to the additional, built on the trigger registers t11.

However, the known converters have insufficient reliability of operation.

The closest to the header is a direct code to additional converter, built on logic elements and adder 2.

However, the design of such a converter is complex enough.

The purpose of the invention is to simplify the device.

The goal is achieved by the fact that in the direct code to additional converter, which contains (n + 1) - bit code and N – N elements and a n-bit adder when converting, each i-ro bit of the input code (.) Is connected with input (1-1) -th element AND-NOT and with input

The i-ro bit of the adder, with another input of which is connected to the output of the i-ro element AND-NOT, the input of the n-th element AND-NOT is connected to the control constant bus, the output of the first element AND-NOT and the bus of the first bit of the input code connected to the inputs of the first digit of the adder, the tire of the sign of the input code is connected to the inputs of all the elements AND NOT.

. The drawing shows a functional block diagram of a direct to additional converter.

The device contains n elements 1-1 g 1-n AND-NOT and p-bit adder 2 (2-1 7 2-p). The first bus sign Ad input code is connected to the inputs of all elements 1-1 t 1-p INE. The second bus of the first bit A of the input code is connected to the input of the first bit of the adder 2-1, ia. The bus of each is the next bit of the input code Ai (2 «i) is connected to the input (AND-NOT element and to input 1- the second bit of the adder 2. One input of the n-th element AND-NOT connected to the (p-And) bus control con output of the n-th element

stanta

I-NB is connected additionally to the transfer input of the n-th bit of the adder.

The converter works as follows.

The input bit code, in the forward code, enters the corresponding inputs of the corresponding bits of the adder 2 and shifts it to the left by one bit of the day and the first inputs of the AND-NOT elements. The receipt of a positive number esro (the digit bit) blocks the NAND elements, which, when the output of the nth element i-PE is connected to the transfer input of the nth digit of the adder, is equivalent to applying 2 signals 0 to the second inputs of all digits, In the outputs of the adder, an input bit code is output without conversion, e.

When a negative number is received, the digit bit of its code () permits operation of all AND-NES elements, and the input number in the forward code and doubled (due to a left shift by one bit) are received at the inputs of the adder. The number in the inverse code from the outputs of the AND elements -NO, and from the output of the lower (nth) element of AND-NOT signal i is fed to the second input and to the transfer input of the lower (nth) bit of adder 2, Adder 2 in this case gives the output number in the additional code, as

D A-2A-E.

If necessary, the conversion of information presented in the reverse code to the input of the nth element of the AND-NOT is constantly fed to the signal H (vmeO).

one hundred signal

The proposed designator is simple and allows the mind to "; Capacity of equipment and power consumed by it.

Claims (2)

1. USSR author's certificate 259472, cl. G About F 5/02. 2.Papernov A.A. logical basis of digital computing. M. Soviet Radio, 1972, p. 163, fig. 18 (prototype).