SU634275A1 - N-digit binary number adding arrangement - Google Patents

Description

The main input of which is connected to the information input of the first prohibition element, the output of the sign bit of the counter and the information input of the third prohibition element, the outputs of the first and second prohibition elements are connected to the inputs of the OR element, the output of which is connected to the information input of the fourth prohibition element and to the first the input element And, the outputs of which are connected respectively to the summing and subtracting inputs of the counter, the control input of the third prohibition element is connected to the device synchronization bus, and the output - to the input of the sign bit of the adder, which is also the sign input of the device, which controls the input of the fourth prohibition element and the second input of the element I.

The drawing shows the functional diagram of the device.

The device contains a n-bit adder 1, the inputs of which bits are the inputs 2 of the device, and the OUTPUT - the outputs of the 3 least significant bits of the device. The output of the sign bit of the adder 1 is connected to the control input of the prohibition element 4 and to the information input of the prohibition element 5. The outputs of elements 4 and 5 are connected to the inputs of the element OR b, the output of which is connected to the information input of the prohibition element 7 and to the first input of the AND 8 element The outputs of elements 7 and 8 are connected respectively to the summing and subtracting inputs of the reversing counter 9, m of which numeric and one sign bits are connected to the outputs of the 0 most significant bits and the output of 11 sign bits of the device. The output of the sign bit of the reversible counter 9 is connected to the control input of the prohibition element 5 and to the information inputs of the elements of the ban 4 and 12, and the control input of the element of the ban 12 is connected to the input (bar) 13 of the device synchronization and the output to the installation inputs of the sign bit of the adder 1. Input 14 digit bit of the device is connected to the input of the sign bit of the adder, to the control input of the prohibition element 7 and to the second input of the And 8 element.

The device allows summing up arrays of numbers by algebraically adding the next (K + 1) -th (n +) -size input c, tagged, sent to inputs 2, 14 of adder 1 with the result of adding previous K numbers stored in adder 1 and a reversible counter. 9. Input terms can be positive or negative. A device containing gp + l numeric bits, in the most unfavorable case (numbers of one sign and maximum are added but not modulo) allows the addition of 2 (n - f - 1) - bit (including sign bit) input binary numbers.

As a result of the summation of the (Kf 1) -th term and in the adder 1 of the lowest n numerical bits, it is possible both positive and negative overflow of the adder, which should be fixed (; the signs possible to change the sign of the number in the adder I relative to the sign of the number in the reversible counter 9. This fact must also be recorded in the counter 9 and bring the sign of the adder 1 in accordance with the sign of the result obtained in the device when summing (K 4 1) -th term.

Denote by

"A - (n + 1) -display number representing the younger n number and sign bits of the K-th sum result. The sign of the number "a" stored in the (n - | - 1) th de-adder 1, before the submission of the next term, coincides with the sign of the result of the previous summation;

“B is the next (n + 1) -discharge term, arriving at the inputs 2, 14 of the device;

 A (t + 1) -display number representing the highest m number and sign digits of the K-th summation. The weight of QQ from P1 numeric bits is 2.

There are four possible cases of transfer from adder i to reversible counter 9 depending on the signs and absolute values of the numbers a, b, c.

1. with 0, a 0, 0 0 and a -f 0 2. In this with ... the result of a-f in exceeds the accumulator grid of the adder 1. A transfer occurs from the n-th accumulator of the adder to (n + 1) -th (sign) bit must be received on the summing input of the counter. This case is illustrated by the following example, in which clause 3, m 4 is adopted. Kn.) Kn. Si. A)

 0.100 is the result of the K-th addition;

O.LO (в) - (К 4- 1) -th addendum

0.0011 UJ.010

- formation of the nose periI and addition in the counter (obtaining the result of (K + 1) -th addition);

about .010

0.0100

Claims (5)

1.Fi.shppov A.G. and Belkin O.S. Designing the logical nodes of the computer-M., “Soviet radio, 1973, p. 263. 2. Authors certificate of the USSR Up to 315179, cl. G 06 F // 50, 1970. 3. Authors certificate of the USSR .. 9 351214, cl. G 06 F 7/50, 1970. 4. Shalaginov Yu. V. The high-speed accumulator of the accumulating type - “Avtometri, 6, 1973. 5. Makarevich, O. B., and Surkova, L. M. A device for inputting initial information into a digital. Integrating machine - Lime by universities, Electromechanics, No. 10, 1969. p. 1070. one