SU1383356A1 - Multichannel priority servicing device - Google Patents

Abstract

The invention relates to the field of automation and computing, and more specifically to devices for priority service of requests with variable priorities, and is intended for use in computing and control systems. The aim of the invention is to reduce the amount of equipment. The device has two priority nodes 3, 5, the encoder 4, the element OR 6, the element AND 7, and in each channel 8 there is a block of elements AND-HE 9 and a comparison circuit 10. This allows to significantly reduce the amount of equipment in the device, to increase the speed and also to expand its functionality and scope by issuing information about the value of the priority code of the highest priority requesting subscriber. 2 Il.

Description

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The invention relates to automation and computing technology and is intended for use in computing and control systems.

The purpose of the invention is to reduce the amount of equipment.

FIG. 1 shows a block diagram of the device; in fig. 2 is a priority node diagram.

The device contains registers 1, decipherors 2, priority node 3, encoder 4, priority node 5, element OR b, AND 7 element, channels 8, each of which contains a block of 9 AND-NOT elements and comparison circuit 10, request inputs 11 , code 12 and signal 13 outputs.

Each of the nodes 3 and 5 contains (Fig. 2) the elements OR NOT 14, the elements 15, the inputs 16 of the node, the subgroups 17 of the inputs of the node, the outputs 18.

The device works as follows.

Priority codes for service requests are entered into registers 1 and are recorded in them. The highest priority corresponds to the maximum code value. Matching priority codes in multiple registers 1 is allowed.

The priority code, located in the corresponding register 1, in the presence of a request signal at the device input 11 of the same name, passes with inversion through the control input block 9 of the AND-N channel elements of the same name to the first input group of the circuit 10 comparing this channel, and is decoded with the same name decoder 2. In the absence of a request signal (zero at the corresponding input 11 of the device), the control inputs of the block 9 of the N-channel elements of the same channel and the work of the decoder 2 of the same name are prohibited, as a result of which and the first group of inputs of the circuit 10 comparing the channel of the same name receives a code with units in all bits, and at all the outputs of the same-name decoder 2, zero signals are generated.

The same outputs of the decoders 2 are combined according to the installation scheme OR on a common bus. Therefore, if there is at least one request signal, a single signal is generated at the device inputs 11 on the corresponding bus.

In general, single signals can form on a group of women. Node 3 positionally allocates one single signal present on the upper bus and corresponding to the maximum code of all codes in the registers 1, which correspond to service requests. The encoder 4 encodes a single signal allocated by node 3, forming a binary priority code of the priority requesting subscriber at the device outputs 12. The generated code is fed to the second groups of inputs of the circuits 10 comparison

of all channels that are detected, in which exactly "active registers 1 (to which service requests correspond) is the code of the highest priority. Node 5

positionally highlights the most significant single signal present at the output of the lowest-numbered channel comparison circuit 10 (with the same and maximum priority codes of the subscribing subscribers

the preference is given to the subscriber to whom the channel with the smallest number corresponds) and gives it to the corresponding output B of the device. Moreover, AND 7 is open with a single signal from the output of the OR B element and does not prevent the signal from being output to the first

output 13 of the device.

The elements OR b and And 7 are introduced in order to prohibit the formation of a false single signal at the first output 13 of the device in the absence of service requests,

when single signals are present on all inputs of the first groups of inputs of the comparison circuit 10 of all channels, and zero signals on all the outputs of all decoder 2, on all outputs of node 3 and the equalizer 4, on the second input groups of the comparison circuits 10

all channels and the output element OR b. Circuits 10 of comparison of all channels give out single signals, and node 5 selects the highest unit at its first (top, in Fig. 1) output, but this unit does not pass to the device output 13i, since the element

And 7 is closed with a zero signal from the output of the element OR 6.

Claims (1)

Invention Formula A multichannel priority service unit containing a group of n registers (n is the number of requests), a group of n decoders and two priority nodes, the output group of each register is connected to a group of information inputs of the same name decoder group, the same names of the output groups of the group decoders are combined according to the scheme OR is connected to the inputs of the first priority node, each request input of the device is connected to the control the input of the same name decoder group, the outputs of the channels are connected to the inputs of the second priority node, the outputs of which, starting with. the second, are the signal outputs of the device, characterized in that, in order to reduce the amount of equipment, it contains an encoder, an OR element, an AND element, and in each channel, a block of NAND elements and a comparison circuit, with the output group of each group register connected to the input group of the NAND element block of the channel of the same name, each request input of the device is connected to the control input of the block of the NAND elements of the same channel, the group of outputs of the block of the elements of the NAND of each channel is connected to the first the group of inputs of the comparison circuit of its channel, the output group of the first priority node is connected to the input group of the encoder, the output group of which is the group of code outputs of the device and connected to the input group of the OR element and to the second groups of inputs of the comparison circuit of all channels, the output of the comparison circuit each channel is the channel output, the first output of the output group of the second priority node is connected to the first input of the element And whose output is the signal output of the device, the second input of the element AND is connected to the output OR element. 17.4  18t, 1  18 -  18 k + rns - / vх-г