SU1485241A1 - Multichannel priority service unit - Google Patents

Description

The invention can be used in computing, in particular in multiprocessor computers and

The invention relates to computing, namely, devices for priority service requests with variable priorities, and can be used in multiprocessor computers and information computing systems.

The purpose of the invention is to expand the scope of the device by organizing asynchronous service requests.

The drawing shows a block diagram of the device.

The device contains a group of registers 1, a group of elements AND 2, a group of elements OR 3, a group of elements AND-OR 4, a group of elements AND 5, request inputs 6, channels 7, each of which contains a decoder 8, a group of elements OR 9, an element NOT 10 , Element 11, Outputs 12 and Element OR 13.

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information and computing systems. The purpose of the invention is to expand the scope by organizing the service of asynchronous incoming requests. The device contains two groups of elements AND, a group of elements OR, an element OR, a group of registers, a group of elements AND-OR and channels, each of which contains a de-4 encoder, a group of elements OR, element NOT, element I. The device ensures the possibility of service asynchronously incoming requests, organizes the discipline of service at each point in time. · 1 Il.

The device works as follows.

Service priority codes are entered into registers 1 and are recorded in them. The highest priority corresponds to the maximum code. Asynchronous service requests are allowed and, moreover, the priority codes in several registers coincide in any service cycle. Requests are serviced in strict accordance with their priority codes in each service cycle. The service cycle ends with servicing a low priority and the next cycle begins.

The priority code, located in the corresponding register 1, is decoded by the corresponding decoder 8 of channel 7. In the absence of a request signal (on the corresponding input 6, a logical zero) on all outputs of the dec

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encoder 8 there are logical units. If there is a request, the decoder 8 generates a logical zero at the corresponding output, but the remaining outputs of the decoder 8 at the same time preserve logical units.

The device, providing service asynchronous requests, organizes the discipline of service at each point in time. This is provided as follows.

Requests received in the initial period of time pass through the elements AND-OR 4 and at their outputs appear signals of the logical unit, which, acting on the inputs of the element OR 13, lead to the formation of a logical unit at its direct output and logical zero at the inverse output. At this moment, the so-called self-capturing of the logical unit is produced in the AND-OR 4 elements, leading to the steady state of the logical unit at the output of the corresponding AND-OR 4. The signal of the logical unit from the output of the OR 13 element is fed to the inputs of the AND 5 elements, thus opening them to pass the request signal from the outputs of those AND-OR 4 elements that have logical unit signals at their outputs. The request signals, fixed by AND-OR 4 elements, through the corresponding AND 5 elements arrive at the control inputs of the corresponding decoders 8, on the corresponding outputs of which a logical zero signal appears. The signal of logical zero, corresponding to the highest priority code, is fed to the input of the first element And 2. The signal of logical zero, corresponding to the lower priority code, is fed to the input of the last element And 2. Thus, the direct outputs of the elements And 2, to the inputs of which received logical zeros decoded priority codes received for service requests, signals of logical zero are generated, and inverse outputs are signals of logical units. The logical unit from the inverse output of the highest priority code temporarily blocks the action of logical zeros of lower priorities on the inputs of the OR 3 elements. Thus, the outputs of the OR 3 elements will contain only one logical zero corresponding to the highest currently accepted priority request. The coincidence of logical zeros from the output of the corresponding decoder 8 and from the output of the corresponding element OR 3 at the inputs of the corresponding element OR 9 will lead to the formation at its output also a signal of a logical zero, which, entering the inputs of the elements And 11 and lower priority channels, closes them, and , arriving at the input of the element NOT 10 of the channel of the same name, is inverted and passes through the corresponding element 11 and to the output 12 of the device. If there is a higher priority code simultaneously in several registers in the same service cycle, logical zeros will go simultaneously to the inputs of several elements NOT 10, however, due to the presence of connections from the outputs of elements OR 9 to the inputs of elements 11 of all lower channels 7, the logical unit will be formed only on one output 12, the number of which will be the minimum among the channels that simultaneously contain the maximum priority codes and put up requests.

After completing the maintenance of the selected channel, the device, upon removal of the corresponding request, proceeds to service the next request. If there are requests from other channels with the same priority as the served request, then the signal of logical zero at the output of the corresponding And 2 element is not removed. Since a logical zero is set at the control input of the decoder 8 of the serviced channel, then its outputs will contain the signals of the logical unit, i.e. the element OR 9 of the older channel will be activated. If there is at least one of the same priority code, its blocking will occur in the same way as when servicing the first request.

After completing the service of the lowest priority request in the first service cycle, the outputs of all AND-OR 4 elements will generate logical zero signals, which will form a zero signal at the direct output of the OR 13 element and a logical signal

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units at inverse output. The logical unit opens the element AND-OR 4, through which the newly received service requests will be fixed. These requests will be serviced in the second maintenance cycle in the same manner as in the first maintenance cycle.

Thus, the device allows you to organize the service asynchronously incoming requests.

Claims (2)

Claim A multichannel priority service device containing a group of registers, a group of elements OR, and in each channel a decoder, with a group of outputs of each register of the group connected to a group of inputs of the decoder of the same name channel, characterized in that in order to expand the scope by organizing service of asynchronous incoming requests , it contains a group of elements AND-OR, two groups of elements AND, an element OR, and in each channel - an element of KE and a group of elements OR, each request input device connected en with the first and second inputs of the same-name element of the AND-OR group, the third inputs of the elements of the AND-YLI group are connected to the inverse output of the OR element, the direct output of which is connected to the fourth inputs of the AND-OR group elements, the fifth input of each element This AND-OR group is connected to the output of the same element AND-OR group, to the first input of the same name element AND of the first group and to the corresponding input of the OR element, the direct output of the OR element to the second inputs of the AND elements of the first group, the output of each of which is connected to Τθ control input of the decoder channel of the same name, ί-th output of the decoder of each channel (ΐ = 1, ..., η, η number of channels) is connected to the corresponding input of the ΐ-th element 15 of the second group and with the first input of the ΐth element OR of the group of its channel, the second input of the first element OR of the group of each channel is connected to the direct output of the first element AND 2d of the second group, second entrance (3 = 2, ..., n) of the OR element of the group of each channel is connected to the output of the §-th (§ = 1, ..., n-1) element of the OR group, the direct output of the third element AND the second Group 25 is connected to the first input of the third element OR group, the inverse output of each element AND the second group is connected to the corresponding inputs of all subsequent elements OR dead bodies, the outputs of the elements OR groups of each channel are combined and connected to the corresponding inputs of the AND elements of the following channels, and through the element NOT with the corresponding input of the element AND of its channel, the output of the element NOT of the first channel is connected to the first and second inputs of the element AND of the first channel, the outputs of the elements AND of the channels are the outputs of the device. 1485241