RU1800605C - Matrix switching device - Google Patents

Abstract

The invention relates to discrete automation and computer technology and can be used in data transmission systems. The matrix switch provides the ability to priority switching channels. The matrix switch contains a clock generator 1, polling blocks 2.1, 2.2, 2.3, a boot matrix 3, a forward switching matrix 4, a reverse switching matrix 5, internal communications 6-9, a group of code inputs 10.1, 10.2, 10.3, a group of response inputs 11, a group of request inputs 12, a group of information inputs 13 of a forward channel, a group of information outputs 14 of a return channel, a group of information outputs of a channel (15), 1 group of information inputs 16 of a reverse channel. 4. ill.

Description

yul

10.2

10.3

00

oh oh oh oh

The invention relates to discrete automation and computer technology and can be used in data transmission systems.

The purpose of the invention is to expand the functionality of the device by providing priority channel switching capabilities.

In FIG. 1 shows a block diagram of a device; in FIG. 2 is a block diagram of a polling unit; Fig. 3 is a structural diagram of a loading matrix; Fig. 4 is a structural diagram of a forward switching matrix and a reverse switching matrix.

The matrix switch (Fig. 1) contains a clock generator 1, polling units 2.1-2.3, a loading matrix 3, a forward switching matrix 4, a reverse switching matrix 5, internal communications 6-9, a group of code inputs 10.1-10.3, a group of response inputs 11, a group of request inputs 12, a group of information inputs 13 of the forward channel, a group of information outputs 14 of the reverse channel, a group of information outputs 15 of the forward channel, a group of information inputs 16 of the reverse channel.

The polling unit 2 (FIG. 2) contains a counter 17, a first decoder 18, a group of group elements AND 19.1-19.4, a group of registers 20.1-20.4, a group of elements OR 21.1-21.3, a second decoder 22.

The load matrix 3 (FIG. 3) contains a group of elements OR-NOT 23.1-23.3, a group of elements AND 24.11-24.43, a group of triggers 25.11-25.43, an element OR-NOT 26, an element NOT 27.

Forward switching matrix 4 (Fig. 4) contains a group of OR elements 28.1-28.3 and a group of elements AND 29.11-29.34, and a reverse switching matrix 5 contains a group of elements OR 30.1-30.4 and a group of elements AND 31.11-31.34.

The group of response inputs 11 of the device is connected respectively to the first group of inputs of the loading matrix 3, the first group of outputs of which is connected respectively. the first groups of inputs of the matrices are forward 4 and reverse 5 switching. The group of information inputs 13 of the forward channel is connected respectively to the second group of inputs of the matrix 4 of direct switching, the group of outputs of which is connected respectively to the group of information outputs of the 15 direct channel. The group of information inputs 16 of the reverse channel is connected respectively to the second group of inputs of the matrix 5 of the reverse switching, the group of outputs of which is connected respectively to the group of information outputs 14 of the reverse channel, Group request

the inputs of the device 12 are connected to the second group of inputs of the loading matrix 3, the second group of outputs of which is connected respectively to the second inputs of the polling units 2, the first inputs of which are connected to the output of the clock generator 1. The group of code inputs 10 of the device are connected respectively with the input groups of the group of polling blocks 2, the group of outputs

0 of which are connected respectively with the input groups of the loading matrix 3. In each block 2 of the survey j-, M, M is the number of input channels of the switch), the group of inputs 10J is connected respectively to the information inputs of the register 20.J, the group of outputs of which is connected respectively to the group of information inputs of the group element AND 19.J. The group of outputs of the latter is connected respectively with the j-th inputs

0 corresponding elements OR 21, the outputs of which are connected respectively to the inputs of the second decoder 22. The group of outputs of the decoder 22 is connected, respectively, to the group of outputs of the block 2 of the sampler, the first 6 and second 8 inputs of which are connected respectively to the counting input and to the input of the unit to the zero state counter 17. The group of outputs of the counter 17 is connected respectively to the group of inputs

0 decoder 18, the j-th output of which is connected to the control input of the group element And 19.j. The first group of inputs 11 of the loading matrix 3 is connected respectively to the R-inputs of the triggers 25 of the corresponding column of the loading matrix 3, the inverse outputs of the triggers 25 are connected to the second inputs of the corresponding elements AND 24 of the loading matrix 3, the outputs of which are connected to the S-inputs of the corresponding triggers 25 matrix 3 downloads. The direct outputs of the triggers 25 of the column of the load matrix 3 are connected respectively to the inputs of the corresponding element OR NOT 23, the output of which is connected to

5 by the third inputs of the elements AND 24 of the corresponding column of the same name matrix 3 loading. The output of the first element OR 23.1 is connected to the second input of the element AND 26 and to the input of the element 27, the output

0 which is connected to the fourth inputs of the AND 24 elements of the second column of the load matrix 3. The output of the second OR-NOT 23.2 element is connected to the first input of the AND-NOT 26 element, the output of which is connected to the fourth inputs of the AND elements 24 of the third column of the load matrix 3. The direct outputs of the triggers 25 of the load matrix 3 are connected respectively to the first group of outputs 9 of the matrix 3 load matrix 4 direct (reverse 5) switching contains matrix elements And 29 (32) and a group of elements OR

28 (30), the outputs of which are connected to the outputs of the matrices of direct 4 and reverse 5 switching. The first inputs of the elements 1/1 29 (31) of the columns of the matrix of elements 29 (31) are connected to the corresponding inputs of the second group of inputs 13 (16) of the matrices of direct 4 and reverse 5 switching, outputs of the elements AND 29 (31) of the row of the matrix of elements And 29 ( 31) are connected to the inputs of the corresponding element OR 28 (30) of the group of elements OR 28 (30), the second inputs of the elements AND 29 (31) of the matrix of elements And 29 (31) are connected to the corresponding inputs of the first group of inputs of 9 matrices direct 4 and reverse No.5 switching.

The matrix switch operates as follows.

There are M query sources (input channels) and K query processing means (output channels). Each of the M query sources from the Viewpoint of each of the K processing means has a certain priority (i.e., a certain degree of preference in switching). Moreover, servicing the requests with the previous processing means for the whole system as a whole is more preferable than servicing the request even with the highest priority with the subsequent processing means, since, in the general case, the means of processing requests in terms of their technical characteristics are heterogeneous and the sources of requests are also heterogeneous, for each There is a certain order of priority in processing requests, according to which the maximum efficiency of the system’s functioning is achieved from the point of view of that the criteria for which is assigned to the priority needs. Given the priority of the request sources, they are switched to the request processing means, as a result of which the request sources and request processing means exchange information both in the forward and reverse directions. Using a predetermined code combination, the query processing means determines the end of the exchange of information. As a result, the corresponding switching is destroyed and the query processing means is switched in the general case to a new request source. The figures show a matrix switch with the number of inputs and the number of outputs, but in the general case K and M can be any integers.

Before starting work, the counter 17, the registers 20.1-20.4 are set to the initial (zero) state (the inputs of the installation to the initial state are not shown). Thereafter

by groups of code inputs 10.M.1-10.M.4 (, 3), registers 20.1-20.4 of each polling unit 2 receive codes characterizing the numbers of the request sources, in order of priority for this service facility. These codes are respectively recorded in registers 20.1-20.4. Suppose that the numbers 2,1,4,3 are recorded in the registers 20.1-20.4 of the polling unit 2.2. This means that the second processing means should first process the requests of the second source, then the first and fourth, and then the third sources.

The fact of receipt of requests from sources is identified with the appearance of unit level potentials at the corresponding request inputs 12 of the device.

We also assume that the first means of service is in the service mode of the request (i.e., switching with it is already

0 is set), and the second tool has just finished servicing the request and is in the mode of making a service request (i.e., in the mode of establishing switching) Assume also that at the request inputs of the device 12.3-12.4 there are unit level potentials and the contents of the registers 20.1 -20.4 block 2.2 of the survey is respectively the numbers 2,1,4,3.

0 Since the second tool has finished servicing the request, a pulse appears at the response input 11.2 of the device, which, entering the zero inputs of the triggers 25.12-25.42, sets (confirms)

5 of them in the zero state. The same pulse is transmitted via the device 8.2 to the second input of the polling unit 2.2 and sets the counter 17 to the zero state. Clock pulses from the generator 1

0 clock pulses in communication 6 through the first input of the polling unit 2.2 to the counting input of the counter 17, increase its content. The maximum counter conversion factor 17 is equal to the maximum number of query sources5 (the number of input channels) of the matrix switch. Upon reaching the maximum conversion factor, the counter 17 spontaneously sets to zero. Counter Content

0 17 is decrypted in the first decoder 18, as a result of which single pulses appear at the outputs of the decoder 18, which, in the order of the queue, arrive at the control inputs of the group elements And 19.2, 19.1, 19.4,

5 19.3. Thus, the contents of registers 20.1-204 through the corresponding group elements AND 19.1-19.4 and elements OR 21.1-21.3 are connected to the inputs of the second decoder 22. At the outputs of the second decoder 22, single pulses appear in order of the established priority of service.

In this case, the pulse first appears at the second output of the decoder 22, then at its first, fourth and third outputs. In connection with 7.2, these pulses arrive respectively at the fifth inputs of AND elements 12.24-24.42. Since the first means is in the service mode of requests, from the output of the element HE 27 to the fourth inputs of the elements AND 24.12-24.42 the resolving potential of the unit level is received. The third inputs of the elements And 24.12-24.42 receives the resolving potential of a single level. The third inputs of elements VI 24.12-24.42 also have a resolving potential of the unit level due to the fact that all triggers 25.12-25.42 are in the zero state. Since the potential inputs of the unit level are not present at the request inputs 12.1 and 12.2, pulses will not appear at the outputs of the elements And 24.22 and 24.12. After that, a pulse appears in the connection 7.2.4, which passes through the AND element 24.42 and sets the trigger 25.42 to the single state. The potential of the unit level from the direct output of the trigger 25.42 is inverted in the element OR 23.2 and closes all the elements AND 24.12-24.42. The appearance of a pulse on the link 7.2.3 in this case no longer allows the trigger 25.32 to be set to a single state.

For the matrix switch to work properly, the following inequality must be observed:

T.1 T.23 + T.24 + T.25,

where T.1 is the repetition period of clock pulses from the clock generator 1;

T, 23 - response time of the element OR-NOT 23;

T.24 - response time of the element And 24;

T.25 - trigger time 25.

The potential of the unit level from the output of the trigger 25.42 via communication 9.24 goes to the second inputs of the And 31.24 element of the reverse switching matrix 5 and the I.29.24 element of the direct switching matrix 4 and opens them. Thus, the switching of the fourth request source to the second processing means is established by input 13.4 through AND 29.24, OR 28.2 to output 15.2 in the forward direction and input 16.2 through AND 31.24, OR 30.4 to output 14.4 in the opposite direction.

After the failure of switching 13.4-15.2.16.2-14.4.4, the switching process in the general case of other channels is repeated again.

The technical and economic effect of using the proposed matrix switcher consists in the fact that it allows priority switching of channels, with priority being given to the input channels which is most suitable for each output channel. In the general case, each output channel assigns a different priority to the input channels. This circumstance makes it possible to significantly increase the efficiency of the entire system from the point of view of the criteria of the system in relation to which priority is assigned to requests. Positive effect

5 is especially noticeable in those systems in which there are constant queues of switching requests.

Claims (1)

SUMMARY OF THE INVENTION 0 is a loading matrix, a forward switching matrix and a reverse switching matrix, and the group of response inputs of the device is connected respectively to the first group of inputs of the loading matrix, the first group5. whose outputs are connected respectively to the first groups of inputs of the forward and reverse switching matrices, the group of information inputs of the forward channel is connected respectively to the second 0 by the group of inputs of the forward switching matrix, the group of outputs of which is connected respectively to the group of information outputs of the forward channel, the group of information inputs of the reverse channel is connected 5 respectively to the second group of inputs of the matrix of the reverse switching, the group of outputs of which is connected respectively to the group of information outputs of the reverse channel, the loading matrix contains matrix elements consisting of an AND element and a trigger, a group of OR-NOT elements, an NOT element, an NAND element, the first group of matrix inputs the load is connected respectively to the R-inputs of the triggers 5 of the corresponding column of the loading matrix, the inverse outputs of the triggers are connected to the second inputs of the corresponding elements AND the loading matrix, the outputs of which are connected to the S-inputs of the corresponding triggers of the loading matrix, the direct outputs of the triggers of the column of the loading matrix are connected respectively to the inputs of the corresponding element OR NOT , the output of which is connected to the third inputs of 5 AND elements of the corresponding column of the loading matrix of the same name, the output of the first OR-NOT element is connected to the second input of the AND-NOT element, and with the input of the element NOT, the output of which is connected to the fourth inputs of the elements AND of the second column of the load matrix, the output of the second OR-NOT element is connected to the first input of the AND-NOT element, the output of which is connected to the fourth inputs of the AND elements of the third column of the load matrix, the direct outputs of the triggers of the load matrix are connected respectively to the first group of outputs of the load matrix, each forward and reverse switching matrices contains a matrix of AND elements and a group of OR elements, the outputs of which are connected to the outputs of forward and reverse switching matrices, the first inputs of AND elements of the matrix matrix of elements And connect are connected with the corresponding inputs of the second group of inputs of the matrices of forward and reverse switching, the outputs of the elements AND rows of the matrix of elements AND are connected to the inputs of the corresponding element OR of the group of elements OR, the second inputs of the elements AND matrix of elements AND are connected to the corresponding inputs of the first group of inputs of the matrices switching, characterized in that, for the purpose of priority switching of channels, it additionally contains a clock pulse generator and a group of K (K is the number of output channels of the switch) of the polling units, etc. than i- (, K) code groups input devices connected respectively with a group of inputs the 1st interrogation unit, the band which outputs coupled to i-th inputs of group groups of inputs of the loading matrix, the second group of outputs of which is connected respectively to the second inputs of the group of polling units, the first inputs of which are connected to the output of the clock generator, the group of request inputs of the device is connected respectively to the second group of inputs of the loading matrix, and the polling unit contains a counter, the first and second decoders, a group of M (M is the number of input channels of the switch) registers, a group of M group elements AND and a group of OR elements, the group of inputs of the polling block consists of M groups of inputs, j -, M) the group of inputs of the polling unit is connected respectively to the information inputs of the j-ro register, the group of outputs of which is connected respectively to the group of information inputs of the j-ro group element AND, the group of outputs of which is connected respectively to the j-inputs of the corresponding OR elements, the outputs of which connected respectively to the inputs of the second decoder, the group of outputs of which is connected respectively to the group of outputs of the polling unit, the first and second inputs of which are connected respectively to the counting input and to the input ohms of setting to zero the counter, the group of outputs of which is connected respectively to the group of inputs of the decoder, the j-th output of which is connected to the control input j-ro of the group element I.