SU1260958A1 - Multichannel device for priority control - Google Patents

Abstract

The invention relates to computing and can be used in automatic and automated control systems. The purpose of the invention is to increase the speed of the device by reducing the polling time of channel registers. The device contains a decoder, n channels, in each channel - a register for mj (i 1, n) bits and a priority node that includes an OR element and a group of elements AND, in each of the kdnals, from second to nth, - the second group of elements I. The group of elements is entered into the priority node of each channel. NOT, the group of elements AND - NOT and the element AND of the third group, serving to ensure relative priority between the bits of the registers. In the channels from the first to (n-1) -th, an OR-NOT element is entered, and in the channels from the second to (n-1) -th, an AND element of the fourth group is used to provide absolute priority between the channels. 1 hp f-ly, 2 ill. i (L About with SP 00

Description

The invention relates to computing and can be used for priority control of the maintenance of objects in automatic and automated control systems.

The aim of the invention is to increase speed.

Figure 1 shows the block diagram of many. priority channel control device; FIG. 2 is a block diagram of a priority block.

The device contains a decoder 1, channels 2, in each channel - register 3, priority block 4, element OR NOT 5, block of elements AND 6, element AND 7, group of response devices 8, group of code inputs 9 of the device, inputs 10 of the node and outputs 11 knots, 12 device outputs,

Unit 4 contains the analysis nodes 13, the first of which contains the element NOT 14, the elements 15 and 16, the element OR 17, the remaining analysis nodes contain the element AND 18, the element AND-NE.19, the element NOT 20, the element OR 21.

The device works as follows.

In the initial state, in all bits of registers 3 are written O. In the absence of signals 1 at the inputs 10 of blocks 4 at the outputs of 11 all blocks 4 are zeroes. When the object code is fed to the input 9 of the decoder 1 in accordance with this code, a unit is written to a certain bit of the corresponding register 3. The signal 1 from the output of this register 3 is converted by the element OR-NOT 5 to the level O, which passes directly (or in the second channel through the element 7) to the input of the block of elements AND 6 and thereby prohibits the signal in all channels of the device having lower priority. At the same time, the signal 1 from the output of the register 3 is fed to one of the inputs 10 of the unit 4 of its channel and passes to the corresponding output 12 of the device. At the same time, all the remaining nodes 13 of block 4 are blocked. After the service is completed, the application passed to output 12 through the corresponding input 8 is given a signal resetting the corresponding register bit 3 to 0. In this case, level 1 is at the corresponding input 10 of priority 4 changes to level O.

If in other categories

five

ten

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55

thirty

35

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45

50

2

register 3 is 1, the output of the 4-wire is passed to the signal from input 10, which has the highest priority (smallest sequence number) from among the inputs on which signal 1 is present. If by the time the service ends, the application in other bits of register 3 is not 1, block 4, and the entire device are returned to the initial state. Thus, the device provides absolute priority between groups of objects, the fact that when a request is received from an object of a higher priority group, service for an object of a lower priority group is immediately terminated, and the relative priority between objects of each group, which means that the application passed to the output of the priority node is completed to the end regardless of whether there are other applications in the queue, and after the end of the service, the application to the condemnation is accepted olee a priority of applications are objects schihs group is at this point in the register group,

Claims (2)

1. A multichannel device for priority control, containing a decoder and in each of the channels, except the last, a register, a priority block, an OR-NOT element, moreover, in each of the channels, starting with the second, a block of AND elements, with a group of decoder inputs is a group of code inputs of the device, the information inputs of the channel registers are connected to the corresponding groups of outputs of the decoder, the reset inputs of the channel registers are connected to the group of response inputs of the device, the outputs of each of the channel registers are connected to The signals of the OR-NOT element and the priority block of the channel, the outputs of the priority block of the first channel are the first group of device outputs, the outputs of the priority blocks of channels, starting from the second, are connected to the group of outputs of the block of elements AND of your channel, the outputs of blocks of elements AND channels, starting with the second, are the corresponding groups of outputs of the device, the input of the block of elements And the second channel is connected to the output of the OR-NOT element of the first channel, characterized in that, in order to improve the speed, the device contains in each channel, except the first and the last, the AND element, the first input of the AND element of the channel is connected to the output of the OR element — the previous channel, the second input An element of the channel is connected to the output of an element OR — NOT its channel; the output of the element AND channel is connected to the input of a block of elements AND of the next channel. 2. The device according to claim 1, which means that the priority block contains analysis nodes, the first analysis node contains two AND elements, the OR element and the NOT element, the other analysis nodes contain an element AND-NOT, the element is AND, the element is NOT, the element is OR, with each priority input connected to the same analysis node with the input of the OR element and with the first input of the AND element, and in the first analysis node - with the first input of the first AND element, in the first analysis node, the output of the second AND element is connected to the second input of the first AND element and through the NOT element to the second input of the OR element the analysis node, the output of the first element and the first analysis node and the output of the elements AND the rest of the analysis nodes are the outputs of the priority block, the output of the AND element of each, the analysis node, starting with the second, through the - element of this analysis node is not connected data th node analysis and the corresponding input of the second AND gate first analysis unit, the second inputs of AND-NO element and OR each analysis unit, starting with the second, connected to the output of the OR gate of the previous analysis unit. Editor T. Parfenova Compiled by M. Kudr Shev Tehred L.Oleynik M.Samborska Proofreader Order 5233/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries. 113035, Moscow, Zh-35, Raushsk nab., D. A / 5 Production and printing company, Uzhgorod, st. Project, 4 FIG. 2