SU1259294A1 - Device for calculating ratio of time intervals - Google Patents

Abstract

The invention relates to the field of automation and computing. The device contains two elements AND, a pulse generator, an element OR, a result counter, a reverse shift register and a trigger. With the help of the reverse shift register, the trigger and the elements AND and OR, a sequence of intermediate pulses is formed, the duration of which is determined by the time interval of the divider, and the total number is determined by the time interval of the dividend. Such an approach to calculating the ratio of time intervals allows us to simplify the constructive implementation of the device by eliminating the code combining unit and the additional counter. 1 il. I SL 5 cd f iNd

Description

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The invention relates to automation and computing, and can be used in information-measuring systems for building specialized computing devices with a time-pulse form of information representation.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of an apparatus for calculating the ratio of time intervals.

The device contains the first and second inputs 1 and 2, the first and second elements AND 3 and 4, the pulse generator 5, the element OR 6, the result counter 7, the reversing shift register 8 and the RS flip-flop 9. The reverse shift register is based on the CCD devices, delay lines or scanning optoelectronic register structures.

The device works as follows.

At the initial moment of time, the KZ-flip-flop 9 is set to a state in which a logical one is present at its outputs. This g is computed by applying to its S and R inputs 10 and 11 a logical zero from the output of the element OR bis. Output 12 of the first bit of the reversing shift register 8. The generator 5 gives pulses to the first input of the first element I 3, with a high frequency, the value of which is limited only by the speed of the register 8.

The first and second inputs 1 and 2 of the device simultaneously receive two pulses of positive polarity T1 and T2, the ratio of which must be calculated. At the input 13 of the resolution of the counting of counters 7, a positive potential appears. At this moment the counter begins to count the number of pulses and pauses between them coming through the second element 4 to the counting input 14 of the result counter 7. The logical unit present at control shift input 15 of register 8 causes the reverse shift register B to shift to the right. At the output of the OR 6 element, a logical unit appears at the second input of the first And 3 element and at the S input lRS-flip-flop 9. Forward;

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during trigger 9, a logical zero appears, which supports the inverse output bv of the one state.

5 The pulses from the output of the generator 5 pass through the first element I 3 to the input 17 of the first discharge of the reverse shift register 8, the contents of which linearly increase to the right as it is filled and at the time corresponding to the end of the second time interval T2, so many bits will be excited register 8, how many pulses will pass to its input 17. On the first and second inputs of the second element AND there is a logical unit, which is fed to the counting input 14 of the counter 7 of the result, which encodes the unit.

At the end of the second time interval T2, at the output of the element OR 6, a logical zero arrives at the S input 10 of the RS flip-flop 9 and sets it to a state corresponding to a logic zero at the inverse output 16. This corresponds to that in the first the time interval is laid down one time interval 12. A logical zero is fed to the input 5 of the shift control register 8 and sets it to the left-shift mode, i.e. the contents of register 8, through output 35, stroke 12 of the first bit are successively shifted to the left and entered into register 8 at input 18 of the last bit, and the result counter 7 encodes a two because of the appearance of a logical zero at output 16 of trigger 9. The shift to the left will continue as long as the output of 12 regs, the horn 8 does not have a logical zero, which sets the RS flip-flop 9 to the state corresponding to the appearance of a logical unit at its inverse output 16, which corresponds to. that in the first time interval T two time intervals T2 were laid.

With the appearance of a logical unit at output 16 of trigger 9, the result counter 7 encodes the triple. Register 8 will shift the content to the right until the output of its last bit 19 does not have a logical zero, which corresponds to the investment of three time intervals T2 in the first time interval T1.

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The result counter will count the number of logical units and the delay occurring at the inverse output 16 of the flip-flop 9 until the first time interval T1 at the first input 1 of the device ends and at the output 13 of the resolution of the count of the counter 7 there is a positive potential enables counter 7 of the result of counting signals.

Claims (1)

Invention Formula A device for calculating a time ratio comprising a pulse generator, the output of which is connected to the first input of the first element AND, the second element AND connected by the first input to the first input of the device, the OR element and the result counter, the output of which is the output of the device. Rzdaktor N.Yatsola Compiled by C, Kazinov Tehred, I.Hodanich Yaakaz 5124/48 Circulation 671.Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 592944 is distinguished by the fact that, for the sake of simplicity, it contains a reverse shift register and an RS flip-flop connected by an S input to the output 5 of the OR element and a second input of the first element AND the R input to the output of the first and last input of the reversing register the shift and the output to the input of the shift control 10 of the reverse shift register and the second input of the second element I, the output of which is connected to the counting input of the result counter connected by the input of the account resolution to 15. The first input of the device, the second input of the device is connected to the first input of the OR element connected by the second input to the output of the last bit of the reversing register 2Q shift, the input of the first bit of which is connected to the output of the first element And, Korre.ktor} t, Kolb