RU1809444C - Device for exhaustion of combinations - Google Patents

Abstract

The invention relates to computing and automation. The purpose of the invention is the increase in speed is achieved by the fact that the device contains M AND elements, M counters, M comparison circuits, M + 1 registers, M 1 adders, M-2 OR elements, 2M-3 delay elements, a clock generator, which allows It is possible to implement enumerations of M numbers from an N-element array in accordance with the mathematical function of CNM. 1 ill.

Description

The invention relates to digital computing and can be used to solve combinatorial problems.

The purpose of the invention is to increase speed.

The drawing shows a structural diagram of the proposed device.

The device comprises a clock pulse generator (GTI) 1, M elements And 21, .., 2m, M + 1 registers 31, ..., 3m-n, M comparison circuits 41, -..., 4m. trigger 5, M counters 6i, ..., 6w, 2m-3 of the delay element 7i, ..., 72M-3, M-2 elements OR 81, ..., 8m-2, M-1 adders 9b .. ., 9m-1. In this case, the output of the GTI1 is connected to the first input of the first 2i element And, the output of the i-ro register 3i (i 1, M) is connected to the first input of the 1st A comparison circuit, the second input of the first 2t element And is connected to the output of the trigger 5, installation inputs to the unit and zero of which are connected respectively to the input of the start of the device and the output of the Mth circuit of comparison 4m. The first input J-ro of the element And 2j (j 2, M) is connected to the output (j-1) -ro of the element And and the counting input i-ro of the counter 6j, the output of which is connected to the i-th output of the device and the second input of the i-th comparison circuit 4i, the output of the kth comparison circuit 4k (k 1, M-1) is connected to the second input j-ro of the AND element 2j, the output of which is connected to the input of the k-ro delay element 7k. the output of the r-th of which (p 1, M-2) is connected to the first input of the r-th element OR 8p, the output of which is connected to the clock input of the r-th counter 6p, the installation input k-ro of which is connected to the output of the k-ro adder 9k, the first and second inputs of which are connected respectively to the output of the (M + 1) -th register 3m + 1 and the input of the jth comparison circuit 4j. The synchro-input of the (M-1) -th counter 6m-1 is connected to the output of the (M-1) -th delay element 7m-1 and the input of the (2M-3) -th delay element 72M-3, the second input of the r-th element OR 8Р is connected to the S-ro output of the delay element 7§ (Зл-М. 2М-3), the t-ro input of which 7t (t М 2М-4) is connected to the output of the 1st element OR 8 | (1 2, M-2).

A combination enumerator operates as follows. The unit code is entered in the register Зм + 1. To the registers, 31, 32, .... Zm. as well as meters 6i, 62, ..., 6m

about y

B

sen codes for numbers N, N-1 ..... N-M + 1, respectively. By the START signal, trigger 5, being set to a single state, opens element 2i And and pulses from GTI1 begin to arrive at the counting input of counter 6i. At that moment, when the contents of counter 6i are compared with the code recorded in register 3j, a logic unit signal will appear at the output of comparison circuit 4i. This signal opens the circuit 22 And and the subsequent pulse passing through it increases the contents of the counter 62 by one, and after some time equal to the delay time of this pulse in the delay element 7i, it is rewritten, increasing by one in the adder 9i, to the counter 6i . The process continues until the contents of counter 6t are compared with the contents of register 3i and the contents of counter 62 are not compared with the contents of register 32, i.e. with a code proportional to N-1. In this case, the elements 22, 2z And are open and the subsequent impulse, passing through them, increases the contents of the counter 6z by one. After a certain delay time, the contents of the counter 6z increased by one are recorded in the counter 6a, and still after the same delay time, the updated contents of the counter 62 increased by one are added to the counter 6i.

The process continues until the contents of the 6m counter is equal to N-M + 1, which corresponds to finding the last code combination of C possible on the output buses 1, ..., M. In this case, the high level signal from the output of the comparison circuit 4m overturns the trigger 5 and thereby disconnects the pulse generator 1 from the rest of the circuit.

The speed of the claimed device is determined by the (M-2) -th delay cycles on the elements 71, ..., 7m-1, i.e. the counting frequency is equal to mr / M, where fr ™ is the frequency of the clock generator, M is the number of numbers to be sorted in the N - element array. The speed of the prototype is determined by the pulse rate from the output of the divider 20, which is equal to tY ™ / N. When solving a wide range of practical problems, the condition M N N holds, thus, at equal GTI frequencies, the speed

The claimed device is N / M times higher than that of the prototype.

Claims (1)

Thus, the object of the invention is achieved - increasing the speed of the device, which contributes to the more efficient functioning of complex digital systems, and also favorably distinguishes the claimed device from the prototype. The claims A device for sorting combinations containing a clock generator, M elements And (M is the number of numbers to be searched in an N-element array), M + 1 registers, M comparison circuits, three counters, three delay element and M-2 OR elements, wherein the output of the i-ro register (i 1, M) is connected to the first input of the i-th comparison circuit, characterized in that, in order to increase speed, it contains M-1 adders, from the fourth to the Mth counters, 2M-6 delay elements and a trigger, the output of the clock being connected to the first input of the first element And, the second input of which is connected to trigger output, the installation inputs 1 and 0 of which are connected respectively to the start input of the device and the output of the Mth comparison circuit, the first input J-rp of the element And 0 2, M) is connected to the output of the (j - 1) element And and the counting input of the 1st counter, the output of which is connected to the i-th output of the device and the second input of the i-th comparison circuit, the output of the K-th comparison circuit (K 1, M - 1) is connected to the second input of the 1st element AND, the output of which is connected to the input of the Kth delay element, the output of the rth of which (p 1, M-2) is connected to the first input of the rth OR element, the output of which is connected to the clock input of the rth counter, installation the input of the K of which is connected to the output of the K-th adder, the first and second inputs of which are connected, respectively, with the output of the (M + 1) -th register and the output of the j-th comparison circuit, the clock input of the (M-1) -th counter connected to the output of the (M-1) th delay element and the input of the Mth delay element, the second input of the rth element OR the output S-ro of the delay element (S, 2M-3), the input t-ro of which (t M, 2M-2) connected to the output of the 1st element OR (I 2, M-2).