SU1736002A2 - Digital filter - Google Patents

Abstract

The invention relates to automation, computing and measurement technology and can be used, for example, in digital image processing systems for classifying signals according to their correlation and spectral characteristics. The invention chain is the enhancement of functionality by providing

Description

The invention relates to automation, computing and measurement technology, can be used, for example, in digital image processing systems to classify signals according to their correlation and spectral characteristics and is an improvement of the invention according to the authors. Ev, No. 1568213.

 The purpose of the invention is to expand the functionality by providing an additional function of determining the weighted average distance between the input analog and reference signals.

The drawing shows a block diagram of a digital filter.

The digital filter contains a centering unit 1, an implementation interval counter 2, first computing units 3.1-Z.M, ML 3, second computing units 4.1-4. (M + 1), unit 5 comparison. The computing unit 3.1 contains the comparator 6 zero, the computing unit 3.2 - multilevel, the delta modulator 7, the computing blocks .M - the subtractor 8 and the input buffer register 9. Each of the first computing blocks 3.i, i-1.M contains the first 10 and second 11 front edge selectors, rear edge selector 12, element OR 13, counter 14 pulses, output

0

buffer register 15- In the drawing, the outputs are marked 16.1-16. (M + 1) of blocks 3.

Each of the second computational blocks 4.2-4. (M + 1) contains a subtractor 17, a functional converter 18, an adder 19. Computing unit 4.1 contains a functional converter 18. In the drawing, the informational 20 and the clock 21 filter inputs, the third information inputs 22.1- 22. (M + 1) second computational units 4, blocks 23 and 24 of setting the first and second constant code values, first additional outputs 25 of computational unit 4. (M + 1), second additional output 26 of the filter. Multi-level delta modulator 7 in the computing unit

53.2 has an odd number of quantization levels and corresponds to a quantizing characteristic with central suppression of weak signals.

The input of the centering unit 1 is 0 digital filter information input 20. In the first computational blocks 3.i,, M, the inputs of the first selector 10 of the leading edge and the selector 12 of the trailing edge are combined5, the outputs of these selectors are connected to the inputs of the element OR 13, the output of which is connected to the counting input of the counter 14 pulses, the input of which is zeroed to the exit of the second allocator 11 front fron. The outputs of the counter I are connected to the information inputs of the output ufer register 15, the clock input is expensively combined with the input of the second selector 11 of the leading edge and connected to the overflow output of the counter 2 of the implementation interval. Jq

The outputs of the output buffer register 15 of the first computational units 3.1-ZM are the corresponding outputs 16.1.-16.M of the indicated units. All the bit outputs of the multilevel 15 delta modulator 7 of the computational unit 3.2 and the outputs of all the bits of the subtractors 8 of the computational units 3. (M-1) are connected to the information inputs of the input buffer registers 20 9 and the second, the inputs of the subtractors 0 of the computational units 3-3 - 3rd respectively. The outputs of all bits of the subtractor 8 of the computational unit Z.M. are outputs 1b. (M + 1) of this 25th unit. The input of the comparator 6 zero of the computing unit 3.1 is combined with the information input of the multi-level delta modulator 7 of the computing unit 3.2 and connected to the output 3Q of the centering unit 1. The output of the comparator 6 zero is connected to the inputs of the first, the selector 10 of the leading edge and the selector 12 of the falling edge of the computing unit 3.1. The output of the sign bit of the bit outputs of the multilevel delta modulator 7 of the computing unit 3.2 and the outputs of the sign bits of the outputs of the subtractors of the 8 computing blocks Z.Z. Z.M are connected to the inputs of the first selector 10 of the leading edge and the selector 12 of the falling front of the corresponding computing unit 3.2 - Z.M.

In blocks 3.3-Z.M, the first inputs of the reader 45 are connected to the outputs of the input buffer register E, the clock inputs of the registers 9 of the computing blocks 3-3-Z.M are combined with the clock inputs of the multilevel delta modulator 7 of the computing unit 3.2, the counter 2 implementation intervals and are connected to the clock input 21 / filter. The second computational blocks A.2-A, (M + 1) contain a subtractor 17, & the first and second inputs of which are the first and second information inputs of the corresponding block

35

40

50

5 5 Q

five

five

0

0

4, the outputs of the subtractor 17 are connected to the first inputs of the functional converter 18, the second inputs of which are the third information inputs 22 of the corresponding block A. The outputs of the functional converter 18 are connected to the first inputs of the adder 19, the second inputs of which are the corresponding computing unit k. In the computing unit k.1, the first and second information inputs are the corresponding inputs of the functional converter 18, the outputs of which are the outputs of this computing unit.

The outputs J6.1 of the computing unit 3.1,, Л, are connected to the first information inputs of the (1 + 1) -th computing unit 4, (i + 1) and the second information inputs of the 1st block A.1 (except for the block .1), the outputs 16.1 of the computing unit 3.1 are also connected to the first information inputs of the .1 block, the outputs of the computing block, i are connected to the fourth information inputs of the computing block (1h-1). The block outputs (. (H + 1) are the first additional filter outputs 25 and are connected to the first inputs of the comparison block 5, the second information inputs of which and the second information inputs of the computing unit 4. (M + 1) are connected to the outputs of the 2k and 23 task blocks a constant code value, the output of the comparison unit 5 is the second additional output 26 of the filter.

The digital filter works as follows.

The analog input signal x (t) fed to the filter input 20 is subjected to the following processing. By means of the centering unit 1, the constant component is eliminated from the signal x (t) and the signal spectrum is corrected with underlining and suppression of individual frequency bands. In each block 3-i,, M, for a time equal to the implementation interval (s) determined by the sampling frequency T and the division rate N of the counter 2 of the implementation interval, the number l) is calculated; j zeros of the 1st order of the input signal: the first block 3.1 V {the number of intersections of the input signal of the zero level, in the second block 3.2 Bg - the number of intersections of the derivative of the input signal of the zero level, in the third block 3.3 DJ - the number of intersections of the second derivative of the input signal of the zero level, etc. At the end of the implementation interval @, the indicated values of the number of zeros are written into the output buffer registers 15 of block 3 and fed to the corresponding outputs 16.

In the next implementation interval, the resulting sequence производитD;} is processed in the second computational blocks H, which consists in calculating the weighted average distance between the input and reference signals. For this, the growth rate of the number of zeros is determined:

Where

UDR -4

M.

D

one

k 1;

DK-DkM, M; (N-1) -Dk ,, ,,

(one)

N (

, M is the number of zeros of the corresponding order;

) / T - sample size. Then the normalized weighted values of the deviation of the rate of growth of the number of zeros of the corresponding order from the given values are calculated.

SD,

(UDK-AD) 2

G / 360028

the pulse rate, the frequency of which is determined by the sampling frequency of the input signal during delta modulation and corresponds to the absence of an overload on the slope of the centered input signal from block 1. During the interval of the implementation (and) TN in the first block 3.1 using a comparator 6 and

The counter of the AND counter is used to calculate the crossing of the zero-level input centered signals (from plus to minus and from minus to plus). At the end of the implementation interval (s) on the front

15 the front of the pulse from the overflow output counters 2, the contents of counter 14 are recorded in register 15, and counter 1 is prepared for the accumulation cycle. Thus, at the outputs of the register 15 of the block 3.1, the number of zeros of the first order of the DJ centered input signal is formed, which is stored at these outputs during the next implementation interval.

25 In the second block 3-2, the centered input signal is sampled and quantized at a frequency T using a delta modulator 7, the outputs of which generate a sign and

30 absolute value of the input signal increment according to the rule:

 EJ "ENT (E-5 + 0.5), UD

Tb

(2)

 m

.

1 minute

(x) m

Where

- given growth rates (growth rates of the reference signal). Summarizing the sequence of values {Ј and D,, M + 1, allows you to determine the sample value 1., the distance between the input and reference signals in the previous implementation interval

yti

/ THEIR. (3)

K 1

Comparison of the magnitude (with a certain predetermined magnitude of yv (reference signal) allows you to confirm or discard the hypothesis that the input signal x (t) corresponds to a reference signal.

Consider determining the number of zeros of the 1st order of a centered input signal.

From the input 21 to the clock input of the counter 2 arrives continuously after “- EJ“ ENT (E-5

 m

.

1 minute

five

where d

(x) m

d xm x

. (d)

R

0

ENT (-) s (x)

five

O

five

the numerical value of the step

quantization;

his sign;

input count

and evaluating it in moments

discretization;

whole part of value ()

minimum zero step

quantizing. The use of a delta modulator 7 with an odd number of quantization levels, with a constant value of the input centered signal, leads to the formation of a sequence of values of fd Јol and does not change the quantization step. The sequence) 1 corresponds to the first difference of the sampled and quantized centered; input signal, i.e. approximates the first derivative of the specified sig-1 signal. Therefore, a change in sign in the sequence fdwj corresponds to a change in the sign of the derivative and

counted for the implementation interval (#) by the counter 14. At the end of the implementation interval, the pulse from the overflow output of counter 2 accumulates in counter 14, the value is written to register 15, and counter 14 is zeroed, which is prepared for the next

accumulation period. Thus, at the outputs 16.2 of the register 15 of the block 3.2, the number of zeros of the second order D2 is formed, which is stored at these outputs during the next implementation interval.

ten

growth of the number of zeros DI, D, the rate of growth of the number of zeros is equal to the number of zeros of the first order. In blocks 4.k,, M, the growth rate of the number of zeros of k-ro and (k-1) th order arriving at the first and second information inputs of the block 4.k, i.e. the first and second inputs of the subtractor 17. At the outputs of the subtractor 17 of the block 4.k, k-2, M, the signal value is generated

AD,

Dv-d

K-1Frrmirovaniya number of zeros more

7

Let us consider high-order by the example of a block of values of a multilevel delta module 15

V - a i pfirn no ll JVtri

ca 3.k (). Sequence 1I idm j, coming from the outputs

The second information inputs of block 4. (M + 1) from block 23 of assigning a constant code value receive a signal value corresponding to (N-1), where N is equal to the division ratio of counter 2 of the implementation interval. At the outputs of the subtractor 17 this

, , 0 then the block is formed corresponding

ra 7 computational unit 3.2, build- “o. /, P

m value of the velocity -D Dm.., (N-1) -Dvn.

. t

The values of the signals DD “J, M + 1, are fed to the first inputs of the functional converter 18, respectively.

25 of the corresponding block 4.k, to the second inputs of which from the third information inputs 22.k of the corresponding block 4.k the value given is fed

is recorded in register 9, as a result of which, during the sampling period T, the outputs and inputs of register 9 contain the values d and d, entering the inputs of the subtractor 8. The subtractor, 8 carries out the output

those.

i j sk) values

(x v

Yn - 4 KIO oriciMcnrm h | j

forms differential operation V -

(

 d - d. (which corresponds to the formation of the second difference of the discrete and quantized centered input signal. The change in the sign of the signal (from minus to plus and from plus to minus) is counted by the counter 14 during the implementation interval (and) and recorded by the signal from the overflow output of counter 2 at the end of the implementation interval to register 15, and counter 14 is zeroed, thus preparing for a new accumulation cycle. 1 The 3.k blocks (kb 3) work in a similar way, forming a differential operation

vk- xm v (vKX) the rate of growth of the number of zeros

JQ of the reference signal, as a result of which the outputs of the functional converter 18 form a normalized (weighted) value of the deviation of the rate of growth in the number of DOC zeros from the given & U according to expression (2). The functional converter 18 can most easily be performed on a permanent storage device, the first and second address inputs of which are the first and second inputs of the converter 18.

The values of the signals G & P,, k 1.11 + 1, from the outputs of the functional converters 18 are sequentially summed by adders 19: at the inputs of the adder 19 of block 4.2, the value of the signal §D, + $ DЈ is formed at the outputs of the adder 19 of block 4.3 - signal value $ 1) (+ $ D2 + & D and so on, resulting in the first additional STX

rri

-V

K-2.

and counting the change in the sign of the signal, for the implementation interval ©. Therefore, at the inputs l6.k of the register 15 of the computing unit 3.k, the number D of zeros of k-ro is formed, which is maintained at these outputs for the next inter-. shaft implementation.

The growth rate of the number of zeros is defined as follows. In block 4.1, according to (1) the speed value

growth of the number of zeros DI, D, the rate of growth of the number of zeros is equal to the number of zeros of the first order. In blocks 4.k,, M, the growth rate of the number of zeros of k-ro and (k-1) th order arriving at the first and second information inputs of the block 4.k, i.e. the first and second inputs of the subtractor 17. At the outputs of the subtractor 17 of the block 4.k, k-2, M, the signal value is generated

AD,

Dv-d

K-115

5 of the corresponding block 4.k, to the second inputs of which from the third information inputs 22.k of the corresponding block 4.k the value given is fed

growth rate of the number of zeros

Q of the reference signal, as a result of which the outputs of the functional converter 18 form the normalized (weighted) value of the deviation of the rate of growth in the number of DOC zeros from the given & U according to expression (2). The functional converter 18 can most easily be performed on a permanent storage device, the first and second address inputs of which are the first and second inputs of the converter 18.

The values of the signals G & P,, k 1.11 + 1, from the outputs of the functional converters 18 are sequentially summed by the adders 19: at the inputs of the adder 19 of the block 4.2, the value of the signal §D, + $ DЈ at the outputs of the adder 19 of the block 4.3 is formed (+ $ D2 + & D, etc., as a result of which the first additional filter outputs 25 form a signal value equal to (p2 according to (3), i.e., the weighted average distance between the input and reference signals.

5 The value of U2 supplied to the first inputs of the comparison unit 5 is compared with the constant value (coming from the second task unit 24

fixed code value. -When the condition is fulfilled (/ (r), a signal of a logical unit is generated at the second filter output 26, signaling that the input centered and reference signals match with a given accuracy. The accuracy of the specified match is determined by the value yg c of block 2 of the fixed code.

The growth rate of the number of zeros & B | L from their order k is a rapidly decaying function, therefore, to determine the normalized weighted average distance between the input and reference signals, a small number of computational blocks k (usually not more than six) are used.

Respectively, the first and second inputs of the subtractor, the outputs of which are connected to the first inputs of the corresponding functional converter, the second inputs of which are the third information inputs of the corresponding second computing unit, the outputs of the functional converter connected to the first inputs of the corresponding adder, the second inputs of which are the fourth. the information inputs of the corresponding computing block in the first., from the M + 1 second computing blocks, the first and second information I inputs are the corresponding inputs of the functional converter, the outputs of which are the outputs

that with insignificant hardware expenditures it is possible to carry out the ideas of this computational unit and to connect and detect given dinene with fourth information signals, as well as to check the statistics of the inputs of the second of the second calculating j hypotheses, for example, the corresponding blocks, respectively, outputs In view of the input centered signal of the 1st first computing unit, the autoregressive process of a given 25 M is connected to the first informational order of the 1to inputs, except the first,

The second computing unit, respectively, the outputs of the first of the first computing units are connected to the first information inputs of the first and second of the second computing blocks, the outputs of the 1st second computing unit are connected to the corresponding fourth information inputs of the (i + 1) -th second computing unit , outputs (M + 1) of the second

Claims (1)

Invention Formula Digital filter according to aut. No. 1568213, characterized in that, in order to expand functionality by providing an additional function of determining the weighted average distance between the input analog and reference signals, a comparison unit and M + 1 second computing units, the first of which are made on the functional converter (each of M), and the rest on the subtractor, functional converter and adder, the outputs of which are the outputs of the corresponding second computing unit, the first mi and the second information inputs of which are thirty the computing unit are the first additional outputs and are connected to the first inputs of the unit compared, the second inputs of which and the second 40, the information inputs of the (M + 1) -th second computational unit are the first and second buses of the constant value code, the output of the comparing unit is the second additional output. Respectively, the first and second inputs of the subtractor, the outputs of which are connected to the first inputs of the corresponding functional converter, the second inputs of which are the third information inputs of the corresponding second computing unit, the outputs of the functional converter connected to the first inputs of the corresponding adder, the second inputs of which are the fourth. the information inputs of the corresponding computing block in the first, from the M + 1 second computing blocks, the first and second information I inputs are the corresponding inputs of the functional converter, the outputs of which are the outputs of this computing unit and connected to the fourth information inputs of the second of the second computing units j, respectively, the outputs of the 1st first computing unit 5 M are connected to the first information inputs 1to, except the first, the computing unit are the first additional outputs and are connected to the first inputs of the unit compared, the second inputs of which and the second the information inputs (M + 1) of the second computational unit are the first and second buses of the constant value code, the output of the comparing unit is the second additional output.