SU1381489A1 - Device for adding and subtracting numbers in redundant minimal notation - Google Patents

Abstract

The invention relates to the field of computing and can be used to add and subtract numbers in an excess minimum number system. The purpose of the invention is the expansion of functionality, through the organization of the operation of subtraction, increase speed. The device contains in each i-th bit of de trigger with a counting input 1, RS-flip-flop 9, four elements OR 2,10,13, 21, nine elements AND 3,11,12,14,17, 18,19 , 33, HE element 15, input buses 28,22,23,24,25,26, reset bus 27, control bus 30, information output 32, transfers inputs 4,5,6,31, transfers outputs 7,8 ,. subtraction outputs 34,35,36,37,38. The operation of the device is based on the direct subtraction algorithm. The proposed device can be used to build universal arithmetic devices with high speed and noise immunity. 1 il. (L

Description

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The invention relates to computing and can be used to add and subtract numbers in an excess minimum number system.

The purpose of the invention is to expand the functional capabilities of the device through the organization of subtraction, as well as increase the speed of the device.

The drawing shows a functional diagram of the proposed device.

The device contains a counting trigger 1, the element OR 2, the element And 3, input 4 transfer from (g + 5) -th bit, input 5 transfer from () -th bit, input 6 transfer from (g + 5) -th discharge outputs 7 and 8 transfers in (d-2) -th and (d-З) -th discharge, RS-flip-flop 9, element IPI 10, elements 11 and 12, element OR 13, element 14 , element NOT 15 Bypass 16 transfer to (d-1) -th bit, elements AND 17-20, element OR 21, input 22 of the first operand, inputs 23 to 26 of (d-1) -th, (d-2 ) th, (d-3) th and (d-4) th device bits, reset input 27, input 28 second operand, output 29 (d-5) -th bit, input 30 of the subtraction-subtraction control - Nee, entrance 31 of (d-5) -th bit, output 32 of the result, the element And 33 and outputs FOR - 38 subtraction.

 the natural number A in the binary minimum number system can be written as

, c (g), (1)

G 1

where a ,, l

O with r O, .1 with Oir i 1, (2) V (r-2) + (t (r-3) with g 1

The value of p (p-i) determines the power of n-bit minimum codes.

The feature of images in the minimal form is the presence in the general case between two nearest logical units of at least four zeros,

The following subtraction rules can be derived from expression (2):) - (j.4r) 0; (+ (r) -v (r-1) V (r-5); i | Xr) - (r-2) V (r-3); 9 (g) - () (g-3) (y (g-4);

C (r) -i (r-4) v (r-3) + V (r-5). (3) 1

Proceeding from expression (3), we present the subtraction algorithm.

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1. The condition of the r-th, (d-1) -th, (d-2) -th, (r-d) -th and (d-4) -th bits of the subtracted is analyzed, provided that the discharge is decreasing contains a logical unit, if in the rth (d-1) -ohm, (d-2) -th, (d-4) -th, (d-4) -th bit of the subtracted, there is a bit containing the logical unit then we subtract by the rules (3) (it should be noted that only one logical unit is possible in the analyzed bits, which is determined by the form of representation of images in the binary minimum number system). There is a reset to the Og trigger of the nth digit and set to 1 trigger (s) in accordance with the rule.

2. If the analysis of the rd, (r-1) -th, (r-2) -th, (r-d) -th, and (d-4) -th bits of the deductible indicated the absence of a single digit, then the gth bit of a shrinkable is deployed by the rule

f (g) ((g-1) + (g-5), (4)

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whereby the p (r-1) -th trigger will be set immediately to a single state, and the (r-5) -th bit, taking into account the state of (d-5) -th, (rb) -th, The (d-7) -th and (d-8) -th bits of the deductible are either subtracted in accordance with clause 1, or scanned in accordance with clause 2.

The essence of the invention lies in the implementation of this algorithm and application for summation of the RS-flip-flop.

The trigger 1 is designed to analyze and store the result of the analysis of the r-th, (r-1) -th, (r-2) -th, (r-3) -th, and (d-4) -th bits of the subtracted.

The trigger 9 is designed to organize the process of addition and subtraction.

The element OR 2 is designed to sample incoming signals to the S-input of the trigger 9.

Element I 3 is intended to form a transfer signal from the rth bit to the (d-2) -th and (r-d) -th bits of the decremented or one of the terms (depending on the modes of operation).

Element I 14 is intended to connect the nth bit of the second addend when summing the input element OR 2.

The element NOT 15 is intended for locking the elements 11 and 11 when the device operates in the summation mode.,

The element OR 13 is designed to allow and organize the subtraction with a single g-th digit of the decremented or single signal at the input 31,

Element 11 is designed to solve subtraction operations in a single state of trigger 1.

Element And 12 is designed to organize the sweep and reset of the n-th bit in O at zero state 15 of the trigger 1.

The element OR 21 is designed to feed to the counting input of the trigger 1 signals from the inputs 22-26.

the input is in the (d-2) -th bit of the deductible, and the input 8 is in the (d-e) -th bit of the deductible.

The element OR 10 is designed for supplying a reset signal to the P input of the trigger 9.

The device is in the mode of summation; works as follows.

The first addendum, fed to the input 28, is entered in the trigger 9, while the unit 30 is fed to the input 30,. A logical signal that unlocks the AND 14 element. The second term is applied to VY 29 and through the element 14 to the input of the element OR 2 and to the input of trigger 9, as a result of which the output of the signal 32 forms the sum value, and the element 3 forms Signal transfer elements AND 17 - 19 and 33 and 20 pre-20 (d-2) -th and (g-3) -th bits, which are assigned to organize the subtraction according to rule 4, with the element And 17 p expression

() (g) - d (g) 0,

the element I 18 according to the expression С (г) - (. Чг-1) ф (г-5);

the element And 19 in the expression f (g) - (g-2) (X; g-3);

the element And 33 in the expression f (g) -f (g-3) f (g-2);

the element And 20 in the expression ((r) -y (r-4) q) (r-3) -t - (((r-5)

Input 28 is the input bus of the nth bit of the first term or decrement.

Input 30 is a control input bus. When organizing the summation, a logical unit is fed to it.

Inputs 22-26 are the inputs for the r-th, (d-1) -th, (d-2) -th, (d-3) -th, and (d-4) -th digits of the subtracted. Input 22 also serves to feed the g-th bit of the second term to trigger 9 in the summation mode.

Inlet 27 is a waste bus and serves to reset triggers 1 and 9.

Input 31 is the transfer signal input from the (r + 5) th bit.

The output 16 serves as a transfer input to the (r − 1) -th bit during the scanning operation (4) of the subtracted.

The output 29 serves as the transfer input of the B (r-5) -th bit during the scanning operation (4) of the deductible.

Output 7 is the transfer output when summing up the contents of trigger 9 with the signal received at its

the input is in the (d-2) -th bit of the deductible, and the input 8 is in the (d-e) -th bit of the deductible.

The element OR 10 is designed for supplying a reset signal to the P input of the trigger 9.

The device is in the mode of summation; works as follows.

The first addendum, fed to the input 28, is entered in the trigger 9, while the unit 30 is fed to the input 30,. A logical signal that unlocks the AND 14 element. The second term is applied to VY 29 and through the element 14 to the input of the element OR 2 and to the input of trigger 9, as a result of which the output of the signal 32 forms the sum value, and the element 3 forms signal transferred5

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Others are known to be zero, due to the minimal form of representation of numbers, while the elements 11 and 11 are locked O from the output of the element 15.

Thus, the process of summing lasts one cycle, which is by a factor of 1 (T) less than that of the prototype (where T is the duration of one cycle, T is the delay time of the delay element).

The device in the subtraction mode works as follows.

Bus 30 receives a zero signal. The reduced is entered into the trigger 9, the subtracted is analyzed by inputs 22 to 26. If there is no signal at inputs 22 to 26, then the state of trigger 1 is zero, this signal through the element 12, opened by the single state of trigger 9, or the signal to input 31 through Element Ш1И 13 is fed to the element OR 2 (d-1) -th bit and to the input of the 31 (d-5) -th bit, wrapped the trigger of the 9th-th bit. In (d-5) -th bit de trigger 1, after analyzing the corresponding bits of the deductible, it is, let's say, in the unit state, then at the output of the element 11 and 11 there is a signal arriving at the inputs of the elements 17-17 and 33 unlocking their. Depending on the state of the bits being analyzed, the AND 17–20 and 33 elements that are subtracted at the input of one of the two elements AND 17–20 and 33 receive a signal that arrives at the input of the OR 2 element of the corresponding bit. If trigger 9 is in a single state, then the summation operation discussed above will occur.

Claims (1)

Thus, if the deductible and the decremented are served simultaneously, the entire subtraction process lasts two clocks. Invention Formula A device for adding and subtracting numbers in the excess minimum number system, containing in each bit a counting trigger, the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth elements: And, first, second, third, the fourth OR element, and the device reset input is connected to the reset input of the counting trigger, the input of the first operand of the device is connected to the first input of the first element OR to the second, third, fourth inputs of which are connected respectively to the transfer inputs from (), (r + 3) th , (r- | -5) -th bit d in the devices, to the output of the first element OR the first input of the first element I, whose output is connected to the transfer output in the (d-2) -th and (d-3) -th unit of the device, is different, in that expansion of functionality due to the organization of the operation of subtraction and speeding up, an additional RS-trigger and an NOT element are added to it, and the direct output of the RS-trigger is connected by the information output of the device to the second input of the first AND element and the first input of the second OR element, the second whose input is connected to the input transfer from the (r + 5) -th bit of the device, the output of the second element OR is connected to the first inputs of the third and second elements AND, the second input of the second element AND is connected to the forward output of the counting trigger, the second input of the third element AND is connected to the inverse output of the counting trigger, the output of the second element And connect the g 0 5 o " five five To the first inputs of the fifth, sixth, seventh, 1st, and ninth elements AND, the output of the third element AND is connected to the input of the first element OR (d-1) -th bit, the input of the second element OR (d-5) -th bit Yes, and the first input of the third element OR of the nth bit, the output of the first element OR is connected to the S input of the trigger, the output of the third element OR to the R input of the trigger, the second input of the third element OR is connected to the device reset input, the first input of the eighth element And it is connected to the input of the control of addition-subtraction, the second input of the eighth element This AND is the input of the second operand of the device, the output of the eighth element AND is connected to the fifth input of the first element OR, the output of the fourth element OR is connected to the counting input of the counting trigger with the counting input, the first input of which is the input of the readout g-th bit, the second - input (d-1) -th bit, the third - () -th bit, fourth - (d-З) -th bit, fifth (d-4) -th bit, input of the fourth element I is connected with the input of the subtracted (r) -th bit, the first element I - with the input of the (r-1) -th bit, the sixth and seventh elements of And - with the entrances (d-2) - About, (r-З) -th bits, ninth element AND - with the input of (d-4) -th bit, outputs of the fifth, sixth, ninth elements AND are connected to the corresponding inputs of the first elements OR, respectively (r- 5) -th, (d-3) -th, (d-2) -th bits, the output of the ninth element AND is connected to the inputs of the first elements OR (d-3) -th, (d-5) -th bit Dov, the output of the fourth element AND is connected to the third input of the third element OR, the input of the element is NOT connected to the input of the control by addition and subtraction, and the output to the third inputs of the second and third elements I.