SU1272328A1 - Device for performing addition - Google Patents

Abstract

The invention relates to the field of computing and can be used in signal processors for real-time information processing. The aim of the invention is to simplify the device for addition. The goal is achieved by introducing a BANGE element into each bit of the device, which allows to exclude one element of the EXCLUSIVE OR or AND from each bit of the device. The proposed three-stage scheme contains in each discharge six elements of type 2I-2ShSh. At the same time, the logical expressions for the output signals do not change. That is: in this way, a reduction from hardware costs by 15% is achieved without reducing the speed of the device. 1 il. (L

Description

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The invention relates to computing and can be used in signal processors for real-time information processing.

The purpose of the invention is to simplify the device.

The drawing shows a functional diagram of a device bit-and for adding a few 5 ”) operands.

The device contains in each bit EXCLUSIVE OR elements 1–4, elements AND 5–7, elements OR 8 and 9 and element BAN 10, inputs 11-14 of the corresponding bits of the terms, input 15 of the transfer and the previous bit, output 16 next time, outputs 18 and 19 of the double-row result code.

The device works as follows.

T1a inputs 11–14 i-ro bits; binary bits X., Y., Z., W. (i .0, 1, ..., N-1) of the N-bit operands X, Y , Z and W, Signals Xj and. from inputs 11 and 12 are fed to the inputs of the element ISKShOCHA: TOTAL OR 1 and element AND 5, and the signals W- from inputs 13 and 14 on the inputs of the element EXCLUSIVE ID 2. The signal X- ® formed at the output element EXCLUSIVE or 1 and signal c input 13 is fed to the inputs of element 6. The signal from the output of element AND 5 and the signal (X. & Y .; Zy from the output of element AND 6 enters the input of element OR 9. At the output of element OR 9, a transfer signal C is generated. X- (X; ©) Z-, | through output -16 of 1st bit {transferred to (1 + 1) -th digit of device. Signals X, - (i) Z © W from outputs ele, cops EXCLUSIVE SHSh 1 and 2 are fed to the inputs of EXCLUSIVE SHS 3. The signal F, - X (+) © Y © Z © W, formed at the output of EXCLUSIVE OR 3, is transmitted to the first inputs of EXCLUSIVE OR 4 and AND 7 and the prohibiting input BAN 10, the direct input of which receives the signal W. from input 14, the transfer signal transmitted from (i-1) th device bit to the input of the 15th digit, is fed to the second inputs of the EXCLUSIVE SHSh 4 element and the And 7 element The signal FI W, formed at the output of the element BAN 10,

and the signal Ff c, from the output of the element And 7 is transmitted to the inputs of the element OR 8. At the output of the element OR 8, a signal S.-F. is generated, and at the output of the element EXCLUSIVE SHSh 4 - the signal s | & s Sin 5 signals are output to the 17th and 18th i-th outputs of the device, respectively.

Formula of invention

A device for adding, containing in each bit the first, second, third, fourth elements EXCLUSIVE OR, first, second, third elements AND and first, second elements OR, the inputs of the corresponding bits of the first and second operands of the device are connected respectively to the first

the inputs of the first element EXCLUSIVE .OR or the first element AND with the second inputs of the first element EXCLUSIVE OR and the first element AND, the output of which is connected to the first input of the first

the OR element, the second input of which is connected to the output of the second element AND, the first input of which is connected to the first input of the second element ORIGINAL OR and is the input of the corresponding bit of the third operand of the device, the input of the corresponding bit of the fourth operand of the device is connected to the second input of the second element EXCLUSIVE OR exit

which is connected to the first entrance

the third element EXCLUSIVE OR, the second input of which is connected to the output of the First element EXCLUSIVE OR, and the second input of the second element

Q AND, the output of the first element OR is the code of transfer to the next bit of the device, the transfer input from the previous bit of the device is connected to the first inputs of the fourth element EXCLUSIVE OR and the third element AND, the second input of which is connected to the output of the third element EXCLUSIVE SH and with the input of the fourth element EXCLUSIVE OR, the output of the third element AND is connected

0 with the first input of the second element RSHI, the outputs of the fourth element EXCLUSIVE OR, and the second element OR are the first and second output of the two-row device result code,

5 characterized in that, in order to simplify the device, a BAN element is entered into it, the direct input of which is connected to the second input

the second element is EXCLUSIVE OR, its inverse input is connected to the output of the third element EXCLUSIVE

OR, the second input of the second element OR is connected to the barring of the element BAN.

Claims (1)

Claim The device for addition, containing in each category the first, second, third, fourth elements EXCLUSIVE OR, the first, second, third elements AND and the first, second elements OR, the inputs of the corresponding bits of the first and second operands of the device are connected respectively to the first · inputs of the first element EXCLUSIVE .OR and the first element AND and with the second inputs of the first element EXCLUSIVE OR 'and the first element AND, the output of which is connected. To the first input of the first element OR, the second input of which is connected to the output of the second element AND , the first input of which is connected to the first input of the second EXCLUSIVE OR element and is, the input of the corresponding bit of the third operand of the device, the input of the corresponding discharge of the fourth operand of the device ₍ connected to the second input of the second element of the EXCLUSIVE OR, the output of which is connected to the first input of the third element of the EXCLUSIVE OR OR, the second input of which is connected to the output of the first element EXCLUSIVE OR and the second input of the second element AND, the output of the first element OR is the transfer output to the next bit '^ set Property, the transfer input from the previous discharge of the device is connected to the first inputs of the fourth EXCLUSIVE OR element and the third AND element, the second input of which is connected to the output of the third EXCLUSIVE OR element and to the second input of the fourth EXCLUSIVE OR element, the output of the third AND element is connected to the first input of the second element OR, the outputs of the fourth element EXCLUSIVE OR and the second element OR are the first and second output of a two-row code of the result of the device, characterized in that, in order to simplify the device, not the BAN element is introduced, the direct input of which is connected to the second input of the second EXCLUSIVE OR element, its inverse input is connected to the output of the third element EXCLUSIVE OR, the second input of the second OR element is connected to the input of the BAN element.