SU1368873A1 - Operand-shifting device - Google Patents

Abstract

The invention relates to computing and can be used in high-performance information processing systems. The aim of the invention is to reduce hardware costs. The goal is achieved by the fact that in the device for shifting operands containing a group of shift modules 1, a decoder zero and a direct code to additional code converter, the shift module 1 includes a comparison circuit 11, a NOT element 12, an AND-13 element, 15 multiplexers 15 and 16 and node 17 one-way shifts. In addition, the AND-OR element 14 is additionally introduced into the shift module 1 with the corresponding links. 2 Il.

Description

h

(L

& 0.

eo eo so

The invention relates to computing technology and can be used in high-performance information processing systems.

The purpose of the invention is to reduce hardware costs.

Fig. 1 is a diagram of the device for shifting operands; Fig.2 is a diagram of the shear modulus.

The device for shifting operands (FIG. 1) contains a group of shift modules 1, a decoder 2 zero, a forward code converter 3, an additional code, an input A of the device shift value, a device information input 5, a device output 6, a device shift type input 7, group of inputs 8 of the device module number, inputs 9 and 10 of the magnitude of the shift and the resolution of the shift of the modules of group 1.

Shift module 1 (FIG. 2) contains a comparison circuit 11, a NOT element 12, AND-OR elements 13 and 1, multiplexers 15 and 16, a node 17 for one-way shifts, 18 and 19 high and low digits of the shift modulus of the shift module, the input 20 and the blocking input 21 of the first multiplexer 15, the control input 22 and the blocking input 23 of the multiplexer 16 information inputs 24 and 25 and the input 26 of the offset value of the node 17 for one-sided shifts.

The numbers and their letter designations, shown near the harnesses and inputs (Figures 1 and 2), indicate the discharge numbers of groups of bits.

The purpose and functionality of the shear module 1 are identical to the shear module of the known device.

The multiplexers 15 and 16 are identical in structure and function to the multiplexers of the known device, and the one-sided offset node 17 is functionally identical to the one-sided shift node of the known device, given that it does not have a blocking function.

Converter 3 is identical to the converter of the known device. The connection of the information input 5 of the device to the information inputs of the multiplexers 15 and 16 of the 1 group shift modules is made identically to the known device.

The device for shifting the operands performs: CPU - cyclic shift to the right, CL - cyclic shift to the left

0

LP is a logical shift to the right, LP is a logical shift to the left. The codes of the CPU, CL, LP, and LL are equal to the codes of the OS, 10, 01, 11, respectively, installed on the senior and younger digit inputs 7 of the device.

To shift the operand, its code is set at the input 5 of the device. At the device input 4, a shift amount code is set. The code of the shift type of the CPU, CL, LP, LL is set on the inputs 7 of the device. The value of the Mm shift value code can

5 within O - (M-K + t) (N-1). The value of M is the value of the part of the code generated at the higher bits of input 4, the value of m is at the lower bits of input 4, N is the input 5, K is the output of the shift module.

At the output 6 of the device, a shifted operand code is generated, the code of which is set at the input 5.

In the case of equality and at the output of the decoder 2, a logical O is formed, which is fed to the input 10 of all the shift modules 1. If the LP code is set at input 7, then under

0, the action of a logical O on input 10 of each m. Module ensures that a code is transmitted from input 5 to output 6. At the same time, a zero code is generated at the output of converter 3 and inputs 9 of shift modules 1, i.e. the extra code from the zero code is also the zero code. When installed on inputs 7 of the CPU, LP, DL codes, the signal value at the output of the decoder 2 does not affect the operation of the device and the transit code transfer from input 5 to output 6 is provided by transmitting the zero code from input 4 to inputs 9 of modules 1, as well as CPU and CPU input 7.

five

five

0

five

If, or, then the output of the decoder 2 is set to logical 1 and the device operates as follows.

When cyclically shifting to the right in each i-M shift module to the output, the multiplexer 15 transmits signals from the a-th group of bits of the information input 5 of the device, where

but

) i-M if i 7, m - (M-i), in p

otherwise.

and the signals of the b-th group of bits of the information input are transmitted to the output of the multiplexer 16, where

.S

i- (M + 1

N

if i, M + 1

- (M + 1-i), otherwise,

In node 17 of one-way shifts, the code is shifted to the right by bits from the a-th group of input digits 5, by pushing the corresponding right-hand side of the code from the b-th group of input digits 5 of the device into the discharged bits.

As a result, at the outputs of each shift module 1, the required part of the code shifted cyclically to the right is formed.

The set of code parts at the outputs of all shift modules 1 forms a complete code shifted right to the right relative to the code set at input 5.

With a cyclic shift to the left in the converter 3, the code is converted into an additional code.

In this case, thirst for the i-th shift module when the output of the first multiplexer 15 is transmitted, the signals and the groups of bits of the input 5 of the device are transmitted, where.

i- (| - M) if i (- M)

, J iM + i,

otherwise, the signals of the s-group of rads are transmitted to the output of the second multiplexer, where

fi- (- M-I) if i (- M + O

 .

1M + 1-1, otherwise. With numbers 1 and i will be equal:

 / N 1- (

(M + D) if i (- (M-I)) K,

M + 1 + i, otherwise; - M, if i (| - M otherwise.

(f

bl + i,

If, then node 17 of one-way shifts of the 1st shift module transits the code from the output of the multiplexer 15, and, therefore, from the b-th group

As a result, at the output 6 of the device, a code is logically shifted to the left.

formula

50

the invention

Device for shifting operands.

The bits of the input 5 of the device to the output gj contain a group of shear modules, de6 devices.

If, then the code from the output of the multiplexer 15 is transmitted to the output of the node 17 with a shift to the right by.

encoder zero, direct code to additional code converter, shift module contains comparison circuit, NOT element, first AND-OR element, two

0

five

equal to (KT) bits, with the corresponding right-hand side of the code from the output of multiplexer 16 being pushed into the discharged bits, and therefore from the i-th group of the bits of input 5 of the device. As a result, at the output of each shift module 1, a corresponding part of the code cyclically shifted to the left is formed. The set of parts of the code on the outputs of all modules 1 shift forms a complete code, shifted cyclically to the left.

In a logical right shift, the device operates in the same way as in a cyclic right shift with the difference that in the shift modules of the case in question, whose numbers block the output of the first and second multiplexers 15 and 16, and only the second multiplexer 16, since the logical 1 is generated at the output of the I-14 element.

As a result, at the output 6 of the device, a code is logically shifted to the right.

In the case of a logical shift to the left, the device functions in the same way as 0 in a cyclic shift to the left. The difference is that in the 1 shift modules.

0

the numbers of which i (- - M) with and

1h

i (- (M + 1) when, K is performed

blocking the output of the first and second multiplexers 15 and 16, since the outputs of the AND-OR elements 13. and 1A of the shear moduli form a logical one. In module 1, the shift number

Nn

i (: r - M) with and 1- (g - ()) with

 only the output of the first multiplexer 15 is blocked with the formation of logical O at all bits, since only the output of the I-IPI 13 module of the module forms a logical G.

As a result, at the output 6 of the device, a code is logically shifted to the left.

formula

the invention

Device for shifting operands.

containing a group of shift modules, a zero decoder, a direct code to additional code converter, the shift module contains a comparison circuit, the element is NOT, the first element is AND-OR, two

a multiplexer and a one-way SHEET node, the device’s shift value input is connected to the information input of the direct code converter into an additional code, the high and low bits of which are connected to the first input of the comparison circuit and the input of the shift value of the group shift modules, information the inputs of the first and second multiplexers of which are the information input of the device, the inputs of the module number of the device group are connected to the second inputs of the comparison circuits The corresponding group shift modules, the outputs of the one-way shift nodes are the output of the device, the input of the shift value of which is connected to the input of the decoder zero, the output of which is connected to the primary input of the first group of the first element and the KPI module of the group shift, second and third inputs of the first group of the first element And-OR which are connected respectively to the inputs of the bits of the device shift type and to the input of the resolution of the direct code converter to the additional code, and in the shift module the outputs of the first and second multi the lexors are connected respectively to the first and second information inputs of the one-way shear node, the first input of the comparison circuit is connected to the control inputs of the first and second multiplexers, the outputs are Less and More than the comparison circuit are connected respectively to the fourth input of the first group and OR, the second

the input of the second group of which is connected to the output of the NOT element, the input of which is connected to the second input of the first group of the first AND-OR element, the third inputs of the first and second groups of

combined, characterized in that, in order to reduce hardware costs, each shear module contains a second AND-OR element, and in the shear module the outputs of the first and

The second element AND-OR is connected respectively to the blocking inputs of the first and second multiplexers, the first inputs of the first and third groups of the first AND-OR element are combined,

output Equal to the comparison circuit is connected to the first input of the first group of the second AND-OR element and to the second input of the third group of the first AND-OR element, the Outputs More and Less than the comparison circuit are connected respectively to the first inputs of the second and third groups of the second I-SHIII element, the second inputs of the first, second and third groups of which are combined and connected

with the third inputs of the first and third groups of the first I-SHS element, the second input of the first group of which is connected to the fourth input of the third group of the first AND-OR element and to the third input of the third group of the second AND-OR element, the third inputs of the first and second groups of which are combined and connected to the output of the item NOT.

fieL

Claims (1)

Claim A device for shifting operands containing a group of shift modules, a zero decoder, a direct code to additional code converter, the shift module contains a comparison circuit, an element NOT, a first AND-OR element, two multiplexers and a one-way shift node; moreover, the input of the shift value of the device is connected to the information input of the direct code converter into an additional code, the outputs of the higher and lower bits of which are connected respectively to the first input of the comparison circuit and to the input of the shift value of the one-sided shift node of the group shift modules, the information inputs of the first and second multiplexers of which are information the input of the device, the inputs of the module group number of the device are connected to the second inputs of the comparison circuits of the corresponding group shift modules, the outputs of the node One-way shear of which are the output of the device, the input of the shear value of which is connected to the input of the zero decoder, the output of which is connected to the first input of the first group of the first element of the I-IPI of the group shift modules, the second and third inputs of the first group of the first element of the I-IPI are connected respectively to inputs of discharges of the type shift of the device and with the enable input of the direct code converter to the additional code, and in the shift module, the outputs of the first and second multiplexers are connected respectively to the first and second the information inputs of the one-way shift unit, the first input of the comparison circuit is connected to the control inputs of the first and second multiplexers, the outputs of the Less and More comparison circuits are connected respectively to the fourth input of the first group and to the first input of the second group of the first I-IPI element, the second input of the second group of which connected to the output of the element NOT, the input of which is connected to the second input of the first group of the first AND-OR element, the third inputs of the first and second groups of which are combined, characterized in that, in order to reduce In terms of hardware costs, each shear module contains a second I-IPI element, and in the shear module the outputs of the first and second I-IPI elements are connected respectively to the blocking inputs of the first and second multiplexers, the first inputs of the first and third groups of the first I-IPI element are combined, the output Equally, the comparison circuits are connected to the first input of the first group of the second AND-IPI element and to the second input of the third group of the first AND-OR element, the outputs of More and Less comparison circuits are connected respectively to the first inputs of the second and third g rup of the second AND-OR element, the second inputs of the first, second and third groups of which are combined and connected | with the third inputs of the first and third groups of the first AND-OR element, the second input of the first 'group of which is connected to the fourth input of the third group of the first AND-OR element and with the third, the input of the third group of the second AND-OR element, the third inputs of which combined and connected to the output of the element NOT.