SU1254466A1 - Device for comparing two n-bit binary numbers - Google Patents

Abstract

The invention relates to automation and computing and can be used in control and monitoring units. The purpose of the invention is to increase speed. The device contains n input elements AND-NOT, input elements OR-NOT, (n-1) intermediate elements OR, intermediate element OR-NOT, output elements AND-NOT, AND AND OR NOT. At the output i-ro (, 2, ..., p) of the input, the element AND-NOT 1; a signal of a logical unit is generated if, in a given bit, a ,,., and at the output of an i-ro input element OR NOT 2; - if. If in the higher of the non-matching bits, then the logical unit on all inputs of the output element is NOT-5, and the output is greater than 11 devices. If a,, then at the i-th input of the output element, NAND is a logical zero at the output of this element, and at the output Smaller device is a logical one. If A B, then the logical unit at all inputs of the output element And and at the output of this element and the output Equals the device. i (L U1 4 9 th

Description

The invention relates to automation and computing and can be used in control nodes. nor control.

The aim of the invention is to improve the speed of the device.

The drawing shows a diagram of the device.

The device contains n input elements AND-NOT 1, p input elements OR-NOT 2, - 2 „, n-1 intermediate element OR 3 ,, - 3 ,,, intermediate element OR-NOT 4, output elements AND-NOT 5, And 6, OR-NOT 7, the inputs of the bits of the first 8, - 8 „and the second 9, - 9p number l, outputs Less than 10, More than 11 and Equal to 12.

The device works as follows.

The inputs 8, -8 "of the device receive the inverse values of the bits of the first number, the inputs 9 (-9, are the direct values of the bits of the second number, the first bit being the highest. At the outputs of the input elements AND-NOT 1j i- ro bit (, 2, .. n) a signal of a logical unit is formed if in this bit (a is the first number, b is the second), and at the outputs of the input elements OR NOT 2, i-ro bit, if This is a de.

If a., B, then the signals of the logical unit will be at the outputs of the elements AND-NOT 1, and OR-NOT 2 ,, and through all intermediate elements OR 3 - the signal of the logical unit will go to all inputs of the element AND-NOT 5, the output of which (and output Less than 10 devices) there will be a logical zero Logic unit at the output of element 2, will go to the input of the element OR NOT 4, and its output will be a logical zero signal, which will generate a signal of the logical zero at the output of the AND 6 element (and at the exit Equals 12 devices). At the output of the element OR NOT 7 (and at the output of More than 11 devices) there will be a logical unit indicating that AB, ..

 -If a, cb, tones of the outputs of the elements fa AND-NOT 1 | there will be a logical zero, which will result in a signal of a logical unit being set at the output of the NAND element 5 (and at the output 10 of the device); and a logical zero signal at the output of the element And 6 ,. and at the exits

11 and 12 devices, which means that.

If in all higher bits, up to (j-l) -ro inclusive

(, 3, ... n), the equality of bits is fixed, then the signal of the logical unit from the outputs of the AND-NE 1f-1j. Elements is received (via the OR 3 elements, - the inputs of the AND-NOT 5 elements

and AND 6, without affecting their condition,

which will be determined by the ratio of the younger ones, starting with the j-ro bit, similarly to the above.

If A B, then at the outputs of all elements of WL-NOT 2 | - a signal of logical zero, which will result in the appearance of a signal of a logical unit at the output of the element OR-NOT 4. Since at the outputs of all elements AND-NOT 1, - Ij, are signals logical unit, the signal of logical zero will be at the output of the element AND-NOT 5 (and output Less than 10 devices),

and at the output of the element And 6 and at the output of Equal to 12 devices - a signal of a logical unit, indicating that A B.

thirty

Claims (1)

Invention Formula A device for comparing two binary-binary numbers, containing n input elements AND-NOT, the first and second inputs of the i-ro element  NAND, where, 2, ... n are the inputs i-x of the bits of the first and second compared numbers of the device, respectively, characterized in that, in order to increase  speed, it contains n input elements OR-NOT, n-1 elements OR, element OR-NOT, output element AND, output element AND-NOT and output element OR-NOT, with output  the first input element AND-NOT is connected to the first inputs of the output element AND-NOT and the output element AND, the outputs of which are respectively the output Less and Equals  devices and are connected respectively to the first and second inputs of the output element AND-NOT, the output of which is the output More, the device output j-ro input element AND-NOT, 55 where j 2,3, ..., p, is connected to the first input (j-1) -ro of the OR element, the output of which is connected to the j-th inputs of the output AND-NAND and AND elements, 312544664 the outputs ix of the bits of the first and are identical with the (+1) input of the k-th elemental compared numbers of the device OR, where k i, i + 1, ..., n-1, and c are connected respectively to the first i-th input of the OR-NOT element, the output and the second inputs of the i-ro input element of which is connected to the (n + 1) -th input of the OR-NOT cop whose output is 5 output element I.