SU1310841A1 - Adaptive analyzer of probability distribution density - Google Patents

Abstract

The invention relates to the field of computer technology and is intended to analyze the statistical characteristics of random processes under conditions of lack of a priori information. The purpose of the invention is to improve the accuracy of histogram evaluation. The analyzer contains averager 1, subtraction block 2, shaper 3 signal modules, maximum calculation block 4, discriminator 5 characters, synchronization block 6, trigger 7, elements 8 and 15, 16, 16 counters 9, 17, shsh 12,13, digital-analogue converter 10, reference element 11, shift register 14, memory blocks 18, 19, block OR elements 20. The operation of the analyzer is based on an adaptive calculation of the scale of the transformation at the training stage and the calculation of the histogram at the obtained scale at the assessment stage. 2 Il. (L Sdd 00 4: fieA

Description

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The invention relates to computing and is intended to determine the statistical characteristics of random processes under conditions of lack of a priori information, for example, in communication systems for analyzing the distribution of intervals between messages or the distribution of the number of errors in a burst of pulses.

The aim of the invention is to improve the accuracy of histogram evaluation,

Figure 1 shows the structural diagram of the adaptive analyzer in figure 2 - block diagram of the synchronization unit.

The analyzer (Fig. 1) contains averager 1, subtraction unit 2, shaper 3 signal modules, max calculation unit 4, discriminator 5 characters, synchronization unit 6, trigger 7, element 8, counter 9, digital-to-digital converter 10 ,. element 11 comparisons, elements OR 12 and 13, shift register 14, elements AND 15, 16, counter 17, blocks 18, 18 | memory block 19 elements OR.

The synchronization unit 6 (FIG. 2) contains a clock pulse generator 20, a switch 21, counters 22-24, a trigger 25, elements AND 26-28, a delay element 29. The overflow output of the counter 22 is connected to the first output of the synchronization unit 6, the first inputs of the elements AND 26 and 27 are connected respectively to the input and output of the overflow of the counter 22, and the second input of the element 26, the inverse input of the element 27 and the first input of the element 28 connected to the inverse output of the trigger 25, the output of the element 27 through the delay element 29 is connected to the second output, the output of the element 26 and the third output of the synchronization unit 6, the input R of the trigger 25 and the input S of the trigger 30 are connected to the input of the initial installation.

The adaptive analyzer calculates the probability distribution density in two stages: the learning phase and the evaluation stage of the function Wj (.

In the initial state, the analyzer blocks are set to the zero state, and in the synchronization unit 6, the sampling pulses of the signal under study are generated at the first output, and the delayed pulses are at the second output

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These are at a frequency equal to the sampling frequency, and at the third output there are pulses of the clock frequency determined by the speed of the logic elements.

From the learning phase, signal analysis begins.

Calculated in the average 1 current estimate of the average value of M (x)

is fed to the input of the subtraction unit 2, in which the operations of discretization and subtraction are performed, as a result of which the counts of the centered random process are formed at the output.

x (i & t) x (i t) - M (x) The centered bipolar signal in the form of a number of samples is fed to the input of the imaging unit 3 of the signal module, in which the absolute value of these samples is calculated (). When reading each i-ro sample to the input of the maximum calculation unit 4 therein, the operation of comparing the amplitude of the reference (x;) with the maximum reference value (x.) Is permitted by the signal of the control synchronization block.

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from the previously received sample sequence and the larger of these values is stored for subsequent comparison.

Thus, in block 4 of the maximum calculation, the selection and fixation of the maximum is made from the signal units of the signal, which is a characteristic of the range (range of the argument) of the calculated function W (x).

Consequently, the value of (x)., „„ „For the MCCC

gives the measurement scale and the approximation step size l х (х), / K, where K is the number of differential corridors (ordinates) of each of the branches of the function.

Since the determination of the maximum of the values of the sample modules, as a rule, does not require high reliability, the learning stage can be carried out on a small interval T And (0.2-0.3) -Tg, where Tg is the interval for calculating the estimate W (x ), i.e. the duration of the assessment phase.

The evaluation stage is carried out under the initial condition formed at the training stage: information on the expected amplitude range of the function was obtained from the initial current data in block 4 of the maximum calculation, and in block 6 of the synchronization

clock pulses begin to flow to the third output.

The processing procedure in the averager 1, the block 2 of the drive and the driver 3 of the signal module is performed similarly to the learning stage, and in the discriminator 5 the sign of the signal is determined by the sign of the reference.

At the same time, the signals from the first output of block 6 sync. Trigger 7 is triggered by opening element 8 for passing clock pulses to counting input of counter 9, the current values of which output code generates a step-varying voltage at the output of the digital-to-analog converter 10. In this case, the value of each step depends on the value (s),

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connected to the reference input of the digital-to-analog converter 10.

When the AC ratio (x ;,) is fulfilled, a comparison element 11 is triggered, the output impulse of which arrives at the installation input in hera 7, returns it to its original state, which prevents the pulses from being passed to the input of counter 9 of the address.

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At the same time, the pulse from the output of the comparison element 11 is fed to the information input of the register 14 and through the OR element 12 to the clock input, as a result of which a single pulse is recorded in the first cell (section, p d) of the shift register 14, being the read enable signal ( through the element IL 13 and elements 15 and 16) of memory blocks 18 and 18, by a synchronizing signal

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from blocks 18 of writing code by address code L, or 18v of memory into counter 17. Another clock pulse from the third output of synchronization unit 6, arriving at the clock input of shift register 14, shifts a single pulse to the second bit, which is a signal counting resolution for counter 17: its content is incremented by one and becomes (W | v + 1) -. The next signal — from the third digit of shift register 14 — allows this code () to be written into the same t-th cell of blocks 18 or 18, the memory (in accordance with the address code AW,), and the signal from the fourth digit output .osu13108414

There is a reset of counters 9 and 17.

As a result of the learning and evaluation steps in the first and second memory blocks 18, 18, probability density estimates are accumulated according to negative or positive readings of the centered signal.

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Claims (1)

Invention Formula An adaptive probability density analyzer containing an averager, a shift register, a reference element, two counters, a synchronization unit, a sign discriminator, a subtraction unit, a signal module generator, a maximum calculation unit, two AND elements, and the input of the decrementing subtraction unit is connected to the averager input and is the input of the analyzer, the output of the averager is connected to the input of the subtracted subtraction unit and is the average value of the analyzer, the output of the subtraction unit is connected to the input of the discriminator the sign and through the shaper of the signal module are connected to the information input of the maximum calculation unit and the first input of the reference element, the outputs Zero and Less than zero of the sign discriminator are connected respectively to the first inputs of the first and second elements AND, the first and second outputs of the synchronization unit are connected respectively to the clock inputs the subtraction unit and the maximum calculation unit, which is used to ensure that, in order to improve accuracy, two OR elements, two memory blocks, a trigger, a third AND element, and lock element or digital to analog converter, wherein, calculating the maximum block output coupled to an input reference voltage DAC, a digital input coupled to an output of the first counter and address inputs of the first and second storage units, data inputs; which are connected to the output of the second counter, the read enable inputs of the first and second memory blocks are connected respectively to the outputs of the first and second elements I, and the outputs of the first and second memory blocks .5-13 connected to the first and second inputs of the OR block, the output of the digital-to-analog converter body is connected to the second input of the comparison element, the output of which is connected to the installation input to the O flip-flop, the first input of the first OR element and the information input of the shift register, the shift enable input of which is connected to the first element OR, the second input of which is connected to the first input of the third element AND and is connected to the third output of the synchronization unit, the first output of which is connected to the input of the installation in 1 tr ggera whose output is coupled to a second input of the third sixteen element And, the output of which is connected to the counting input of the first counter, the output of the first bit of the shift register is connected to the first input of the second s the OR element and the synchronization input of the second counter, the outputs of the second and third bits of the shift register are connected respectively to the counting input of the second counter and the second input of the second OR element, the output of the fourth bit of the shift register is connected to the inputs of the O and the first and second counters; elements OR connect It is connected to the information input of the second counter and is the output of the analyzer. cftuff. Editor N.Gorvat Compiled by E.Efimova Tehred L.Oleyk 1893/46 Circulation 673 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Production and printing company, Uzhgorod, st. Project, 4 Proofreader M. Pojo