SU1226487A1 - Device for analyzing distributions of random processes - Google Patents

Abstract

The invention relates to computer aids and can be used for statistical analysis of random processes, namely for measuring the probability density distribution. The purpose of the invention is to improve the accuracy of determining the density of the probability distribution. This is achieved by introducing into the device a switch, a registration unit, an AND element, an address counter and a digital filter with corresponding functional relationships between them and known device blocks. As a result of the operation of the device, a Parzen-Rosenblatt estimate (a sod score) is formed for the probability density of the analyzed random process. The type of core (weighting function) is determined by the impulse response of the digital filter. 4 il. § kA

Description

The invention relates to the specialization of computer technology and can be used for statistical analysis of random processes, namely, to measure the probability density.

The purpose of the invention is to increase the accuracy of determining the density of the probability distribution.

FIG. 1 shows a block diagram of a device for analyzing distributions of random processes; in fig. 2 - digital filter block diagram; in fig. 3 is a block diagram of the control unit i in FIG. 4 - time diagrams of signals.

The device for analyzing distributions of random processes (Fig. 1) contains an analog-to-digital converter (ADC) 1, switch 2, memory block 3, combination 1; ionizer 4, element 5, address counter 6, digital filter 7, registration block 8 and control unit 9. The input. Of the device is the I-input input of the analog-digital converter 1., the output of which is connected to the second information input of the switch 2, whose first information input is connected to the output of address B

The output of the switch 2 is connected to the address input of the memory block 3, the information input of which is connected to the output of the element 5, the primary input of which is connected to the output of the adder 4 whose input is connected to the output of the memory block 3 and the information input of the digital filter 7 whose output is connected with information input unit 8 registration. The input of the control unit 9 and the installation input of the address counter 6 are connected to the Start bus. The first output of the control unit 9 is connected to the control input of the analog-digital converter 1, the second dig. the stroke of the control block 9 is connected to the control input of the memory block 3,. the third output of the control unit 9 is connected to the counting input of the address counter 6 and the first control input of the registration unit 8, the fourth output of the control unit 9 is connected to the control input of the digital filter 7, the fifth output of the control unit 9 is connected to the control input of the switch 2, the second control input of the registration unit 8 and the second input of the And 5 element.

The digital filter (FIG. 2) contains the first switching node 10, the memory block 11, the second switching node 12, the summing node 13, register 14 | ,

element 15. The digital filter information input is the first information input of the first switching node 10, the second information input of which is connected to the first input of the AND 15 element and the output of register 14, and also the digital digital output. The output of the first switching node 10 is connected to the information input of the memory block 11 and the first information inputs of the second switching node 12, the second information input of which is connected to the output of the memory block 11. The output of the second node 12 is connected to the first input of the summation node 13, the second input of which is connected to the output of the AND element 15, and the output of the summing node 13 is connected to the HHbnvi information input of the register 14. The control input of the digital filter 7 is formed by the control inputs of the node 10 computations and register 14, the address input of the memory block 11, as well as connection. HeHHbLVM between each other with the control input of the memory block 11 of the control

the input node 12 of the switching and the second input element And 15.

The control block 9 (Fig. 3) contains the first and second generators 16 and 17 clock pulses, the first ;, the second

and the third elements 18-20, the first, second, third and fourth counters 21-24, the RS-trigger 25 and the switch 26, the output of the first generator 16 clock pulses connected to the second input of the first element 18, the first input of which is connected to the control the input Ko: NfMyTaTopa 26 and the output of the trigger 25, and the output of the first element I 18 is connected to the second information input of the switch 26 and the counting input of the first counter 21, the output of which is connected to the R input of the trigger 25, the inverse output of which is connected to the first input of the second

element And 19. The output of the second generator 17 clock pulses connected to the first input of the third element And 20 and the input of the third counter 23, l. luzhd which is connected to the input of the first counter 24, the first output of which is connected to the second input of the second and second (inverse) input of the third elements And 19 and 20, the output

The third element And 20 is connected to the input of the second counter 22. The first output of the control unit is the output of the first element And 18. The second output of the control unit is the output of the switch 26. The third output of the control unit is the output of the second .I element 19 and the first the information input of the switch 26. The fourth output of the control unit is formed by the output of the second element I 19, the output of the second 17-clock pulse generator, the output of the third counter 23, and the bit outputs of the second and fourth counter 22 and 24. The fifth output of the control unit is the direct output of the trigger 25. The setup input of the first counter 21 and 5 is the input of the trigger 25 connected to the Start bus.

FIG. 4 shows time diagrams of signals on the Start bus and on the fifth output of control block 9 (Y), and in playback mode: the fourth, sixth, second and third outputs of control block 9 (U, U, Uj and 1) 5), and also at the bit outputs of the second and fourth counters 22 and 24 of the control unit 9 (1) i).

A device for analyzing distributions of random processes works as follows.

On a signal from the bus Start, the device enters the accumulation mode: the counter 6 of the address and the first counter 21 of the control unit 9 are reset, and the trigger 25 is set to one. From the output of the first generator 16 clock pulses through the first element I 18 to the control input of the analog-digital converter 1 pulses C are fed with a constant follow-up period T equal to the sampling interval of the implementation x (t) of the random process being analyzed.

In the analog-digital converter 1, the implementation of xCt) is sampled and quantized by level. The digital reading X from the output of the analog-digital converter 1 through the switch 2 is fed to the address input of the memory block 3. The contents of the memory cell block 3 with the address X | enters adder 4, where a unit is added to it, and then the result of the summation through element 5 goes to the information input of memory block 3 and the signal from the second output of control block 9, which arrives at the control input of memory block 3, is stored at the same address u. This is repeated N times.

where N is the number of digital samples from which the probability density measurement is taken.

The device then goes into playback mode. It happens as follows. The pulses U.,, supplied to the control input of the analog-digital converter 1, simultaneously hit the counting input of the first counter 21 of the control unit 9.

The conversion factor for this counter is N. Therefore, after the arrival of the Nth pulse at the control input of the analog-digital converter 1 from the output of the first counter 21 of block 9

control on the R-in of the flip-flop 25, a pulse arrives that sets the flip-flop 25 to the zero state. As a result, at the forward output of the trigger 25, a zero potential is established, at which the pulses from the output of the first element 18 of the control unit 9 to the clock input of the analog-digital converter 1 stop, the switch 2 starts

pass information to exit with

its first information input, and the output of AND 5 is set to the zero state. At the first input of the second element AND 19 block 9 control with inverse output trigger

25, a single potential is supplied through which the third output of control unit 9 from the first output of the fourth counter 24 of the control unit 9 through the second element 19 begins to receive pulses Uj, the follow-up period of which T. is equal to the information reading period from memory block 3. These pulses arrive at the counting input of the counter 6 address. Coefficient,

recalculation of the address 6 counter is equal to N, where Ng is the number of cells in memory block 3 (for example, for a 10-bit analog-digital converter 1 and, respectively, for memory block 9 having 2 cells, the address counter 6 has a conversion factor NQ 1024, i.e., the address counter 6 is a 10-bit binary counter). From the output of the address 6 counter, through the switch 2 to the .address input of the memory block 3, an address code is supplied that varies from 0 to () with a period T. As a result, from the output of the memory unit, periodically with

period t on the information input, digital filter 7 receives digital samples PJ. , each of which is equal to the number of hits of digital samples X j (i 1, ..., N) in j –and interval of levels (j О, ..., N, - 1). At the output of digital filter 7, a sequence of digital samples is formed.

M- P .h

J-0

e-j

where {bf} is the impulse response of the digital filter 7. The expression for 1y can be rewritten in another form:

It can be seen that the sequence | The street is a digital analogue of the nuclear probability density estimates, and the role of the weight function determining such an estimate is played by the impulse response 1; of the digital filter 7. The digital samples alternately with the period T are fed to the recording unit 8, which serves to display the density measurements probability distribution. As a block 8 registration, you can use the alphanumeric printing device, plotter, display and other digital recording devices. The pulses and, arriving at the first control input and having a repetition period T, are used in block 8 of registration for gating digital readings P- arriving at the information input. The signal Uj arriving at the second control input is used to trigger a sweep in block 8 of registration.

Digital filter 7 must have an impulse response that matches the weighting function. As an impulse response, it is advisable to use a rectangular weight window, Bartlett, Parzen, Kolmogorov weight functions, binomial functions, as well as functions close to a Gaussian curve. All these weight functions are implemented by digital filter 7 (Fig. 2).

Digital filter 7 is equivalent to connected cascade and digital filters, each of which has a square impulse response consisting of K samples. therefore

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for n 1, the impulse response h coincides with a rectangular weight function, for h 2 with a Bartlett weight function, and for n 4 with a Parzen weight function; with an arbitrary n-with the Kolmogorov weighting function, with a binomial weighting function of degree q,; as h increases, the impulse response {hj will tend to a Gaussian curve. Digital readings arrive at the information input.

15

20

25

thirty

- 35 -

R

t-3

40

45

50

7 with period T is divided into n equal to PJ

digital filter

Each interval of T intervals of T, each of which, in turn, is divided into 14 intervals of I, where I- is the period of the pulses at the output of the second generator 17 clock pulses. The operation of digital filter 7 at each interval T is equivalent to the operation of a digital filter having a rectangular impulse response bj consisting of K samples:

Gy

C 1;

e

e oh ...

o 5 FOR other e.

Digital filter 7 operates as follows. The digital readout Pj is fed from the output of the memory block 3 to the information input of the digital filter 7 at the time of the pulse U-, which switches the memory block 3 to the information reading mode. The digital readout Pj hits the first information input of the first switching node 10. At the same time, a pulse Uj arrives at its control input, the temporal position of which in playback mode coincides with the temporal position of the pulse U. By the pulse Uj, the digital count Pj passes through the switching node 10 to the information input of the memory block 11 and is stored therein in a cell with a certain address A. In addition, the digital count Pj is fed to the first information input of the second switching node t2. On the pulse Uj, the digital readout PJ passes through the second node 12 to the first input of the synchronization node 13. At the same time, pulse 0 is applied to the second input of the AND element 15 and sets it to the zero state. Therefore, the PJ count goes through the summation node 13 without modification and arrives at the information

The input of register 14. The pulse and digital readout P is stored in register 14. Then the following is repeated until the end of time interval T (K - 1). The contents of register 14, through element I 15, go to the second input of node 13, and to its first input, from the output of memory block 11, from the cells with addresses A, A ,,, ..., And through the second switching node 12, digital samples P are received; By U pulses

information from the output of summation node 13 is mined. As a result, at the end of the interval with duration T

R. R

 4- J-u.

In register 14, register 14 stores the sum K of digital samples P; :

J

i J-K + 1

The digital readout Sj, through the switching node 10, arrives at the information input of the memory block 11. According to the signal U., which sets the memory block 11 to the information recording mode, the digital count Sj is stored in the cell with the address A. Then to the end of the interval of duration T "with the count

S.

the same operations are carried out as with the digital readout on the previous interval T. The difference is only in that the digital readings Sj,, S .. J, j, stored in the memory cell 11 with addresses A, are now summed up. L.

 SK

i-j-K + 1

Digital readout d, which is the result of filtering digital samples from PJ. in two cascade-connected digital filters with rectangular impulse response, is written to register 14.

Then, until the end of the interval T, at each interval T, the same operations are performed as in the first two intervals T. As a result, at the end of the interval T in register 14 it turns out - with a recorded digital sample v, which is the result of filtering digital samples P. in n cascade-connected digital filters, each of which has a rectangular, impulse response consisting of K from the accounts.

Let us now show how the address signals U are generated for block 11

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memory. digital filter 7, which determine the order of recording and reading information. UT address signals are generated in the second and fourth

5 counters 22 and 24 of control block 9. The second counter 22 has a conversion factor of H, and the fourth counter 24 has a conversion factor of h. Counting pulses U arrive at

10 input of the fourth counter 24 from the output of the third counter 23, the conversion factor of which is equal to K. The bit outputs and the fourth counter 24 after the arrival of the next pulse

) 5 and within the interval T increase their state by one: from 0 to (| - .1). Thus, at each time interval T within the interval T, only K of the 20 blocks of the memory 11 belonging to one of the p cascade-connected conventional digital filters are accessed. The counting pulses come to the input of the second counter 22 from the output of the second generator of 17 clock pulses through the third element 20. To the second input of the third element 20 from the transfer output of the fourth counter 24 at the beginning of each interval T., a pulse arrives (coinciding in time with Uj) which prevents the passage of a single-second pulse per interval T from the output of the second generator 17 clock pulses to the counting input of the second counter 22. Therefore, the second counter 22 is at the beginning of each new interval T (and, accordingly, at the beginning x intervals T inside this new interval T) will coincide with the state

 the second counter 22 at the end of the previous interval T (and, respectively, at the end of all the intervals T within this previous interval T). In other words, if on one interval T a digital reading is p. stored in block 11 of memory in a cell with address D, a digital count is stored in a cell with address A, a digital count dy is stored in a cell with

50 address And „.. etc., then in the next interval T digital readout p. memorized in the cell with the address d; digital samples Sj and dj., memorized in the cell with the addresses

55 respectively and A, etc. Consequently, digital readings Pj-.,, S. d-. are placed in block 11 of memory to place

  Sj-k.i dj-K + i (which is no longer necessary for further calculations.

Thus, as a result of the operation of the proposed device, a Parzen-Rosenblatt estimate (turf estimate) is formed for the probability density of the analyzed random process. The type of core (weight function) is determined by the impulse characteristic of the digital filter 7. In the considered version of the digital filter 8, realizations of the square weight function, the weight functions of Bartlett, Parzen, Col10

mogorov and binomial weight functions.

Claims (1)

Invention Formula 15 20 A device for analyzing random process distributions, comprising an analog-to-digital converter, whose information input is the information input of the device, and a clock input connected to the first output of the control unit, the input of which is the start input of the device, the second output of the control unit is connected to the recording control input of the block memory, the bit outputs of which are connected to the bit inputs of the combinational adder, which is so that, in order to increase the accuracy of determining the density, Probably, it contains a switch, a registration block, an AND element, an address counter and a digital filter consisting of a memory block, an And element, a summation node, a register, and the first and second switching nodes, the first information input of which is connected to the output the memory of the device, and the output of the first switching node is connected to the information input of the digital filter memory and the first information input of the second switching node, the second information input of which is connected to the output of the memory block and the output a first summing node input of the digital filter, a second input node sous {mirova- audio connected to the output of the AND digital filter, summing node and the digital filter output is connected to informahschonnym input register, whose output is connected to second data input of the first node 25 1226487 O switching, the first input element And digital filter and connected to the information input of the registration unit, the input of the address counter installation is combined with the input of the control unit, and the output of the address counter is connected to the first information input of the switch, the second information input of which is connected to the output of the analog-digital converter and the switch output is connected to the address of the memory unit, whose information input is connected to the output of the element I., the first input of which is. It is coherent with the output of the combinational cy atopa, while the control unit consists of the first and second clock generators, the first, second, third and fourth counters, the switch, the RS trigger, and the first, second and third elements And The tick is combined with the 5 input of the RS trigger and is the input of the control unit, and the output of the first counter is connected to the R input of the RS flip-flop, the direct output of which is connected to the control input of the switch, with the first one; the input of the first element I of the control unit and connected to the control input of the device switch, the second input of the AND element and the scan start input of the device registration unit: a, and the inverse output RS of the control unit trigger is connected to the left input of the second I element whose output is connected to the first the information input of the switch of the control unit, to the counting input of the address counter, the input of the gate of the registration unit and to the control input of the first switching node of the digital filter, the second input of the first element And the block control unit is connected to the output of the first clock generator, and the output of the first element I is connected to the counting input of the first counter, to the second information input of the switch of the control unit and is the first output of the control unit, and the switch output of the control unit is the second output of the control unit, the output of the second the clock generator of the control unit is connected to the input of the third counter, the first input of the third element I, and connected to the input of the control register of the digital filter register, the output of the rd counter thirty 35 40 45 50 55 and 12 the control unit is connected to the counting input of the fourth counter and connected to the control input of the second switching node, to the second input of the digital filter element I and to the recording control input of the digital filter memory block, the transfer output of the fourth counter of the control unit is connected to 12 the second inputs of the second and third elements of their own unit, the output of the third element and the control unit are connected to the counting input of the second counter, whose outputs and outputs of the fourth counter of the control unit are connected to the address input of the digital filter memory block. HHipopMai uonHbiu Wmd 51 p .JU ™ .. L Nanopmnie Reproduce and Reproduce .f " w .JU ™ .. L .... AND " wrwwifiwfl Editor S. Lyzhov Compiled by E. Sechin Tehred L.Oleynik Proofreader 0. Lugov Order 2136/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. - d. 4/5 Production and printing company, Uzhgorod, ul. Project, 4