SU1654811A1 - Device for extremum filtering - Google Patents

Abstract

The invention relates to computing and can be used. used in digital signal processing systems, for example, for median signal filtering. The purpose of the invention is the expansion of functional capabilities by ensuring the sorting of numbers in a sliding sample. The device contains N analysis cells (N is a moving sample aperture), N buffer registers 2 -2N input register 3, synchronization unit 4 Analysis cell contains registers, switches, comparison unit. Comparison unit contains comparison elements, elements I. A synchronization unit contains a pulse generator, a trigger, element I. 4 ill.

Description

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The invention relates to computing and can be used in digital signal processing systems, for example, for median signal filtering.

The purpose of the invention is to enhance the functionality by providing sorting of numbers in a sliding sample.

Figure 1 shows the layout of the device; figure 2 - diagram of the cell analysis; 3 and 4 are possible schemes of the analysis unit and the synchronization unit.

The device contains N cells 1, –1 analysis centers (N is a sliding sample aperture), N buffer codes 2 {–2ft, input register 3, block 4 synchronization, input 5, and outputs b - 6j. Analysis cell 1 contains registers 7-9, switches 10 and 11, comparison block 12, inputs 13 ,, -133 and outputs 14ts — Comparison block 12 contains elements 15, -15 $ comparison, elements 16 and 17, inputs 18} 184 and the outputs 19.J -193. The synchronization unit 4 comprises a pulse generator 2 trigger 2t, an element K 22 and outputs 23, -233.

The device works as follows.

The input sequence numbers are fed to the register 3 input. When pulses are output from the synchronization unit 4 to the clock inputs of registers 2 and 3, the next number a is written to register 3 and the remaining numbers are overwritten in N registers 2 “From the outputs of registers 3 and

2N numbers aj

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tupagot to the inputs of the first cell were known, for 1 „,, Each cycle of the device operation is divided into two half-cycles - g.e. into two non-overlapping calculation phases. In the first half-cycle, from the output 23 of the synchronization unit 4, the readout inputs of registers 2 and 3 are given a logic O signal. At the outputs of registers 2 there are OR elements, (and when the zero signal is applied, their second inputs read codes of numbers written in these registers In the second half-act upon receipt of the control signal

50In each operation cycle of the device, in the i-th analysis cell 1j, the 1-order statistics of the corresponding sliding sample numbers, which is recorded in register 7 of cell 1, is calculated; . According to the implemented algorithm for recursive calculation of order statistics as the 1st order statistic, which is written to register 7 of cell 1; in the k-th cycle, there may be neighboring random statistics and i-order statistics calculated in (1s-1) -th cycle, or the next number a, from register output 3. If the conditions are met, the number ak can be go through all those cells 1 | for which ak; . Similarly, the number ak from the output of register 2 (4 can pass through cells 1 without change. Since the contents of the registers of the k-th and (kD-th order statistics of neighboring cells 1 are exchanged with register 8), it is executed in the device in two half-cycle (the synchronization circuit of registers 7-9 of analysis cells 1 are not shown.) In each half-cycle, each cell performs the same operations of the contents of register 7 C calculated in the previous half-time, 35 with binary codes X (() and Yk. (formed at inputs 13 and 134 are cells. UK These operations are simultaneously carried out by the comparison unit 12. At the output 19 of the comparison block 12, a logical 1 signal appears if, and on the output 193, it appears in the case of the inequalities Ykwt C and X |, 6 Ck. the inequalities X, Ј. C., and k- (- ki then signal 1 is present at output 19. In this case, binary codes are written to registers 8 and 9, all bits of which are equal to one, i.e. maximum codes, and therefore, when they arrive at the inputs of the cell 1j, the contents of the register 7 of this cell do not change. Thus, after two half-packs

logical 1 reads the l55 operation of the device in the register 7 j-th

cells 1; is recorded in the kth cycle

from registers 2 codes, all binary bits of which are equal to one, i.e. maximum numbers. Write numbers in

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The code of the jth order of the statistics of the sequence of N numbers with respect to

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Register 2 is produced in the first half-cycle.

In each operation cycle of the device, in the i-th analysis cell 1j, the 1-order statistics of the corresponding sliding sample numbers is calculated, the code of which is written to the register 7 of cell 1; . According to the implemented algorithm for recursive calculation of order statistics as the 1st order statistic, which is written to register 7 of cell 1; in the kth cycle, there may be adjacent order statistics and i – order statistics computed in (1s-1) -th cycle, or the next number a, from register output 3. If the conditions are met, the number ak can, without changing go through all those cells 1 | for which ak; . Similarly, the number ak from the output of register 2 (4 can pass through cells 1 without change. Since the k-th and (kD-th order statistics of neighboring cells 1) exchange contents by register 8, it is executed in the device in two half-pulses (the synchronization circuits of registers 7-9 of analysis cells 1 are not shown.) In each half-cycle, each cell performs the same operations of comparing the contents of register 7 C calculated in the previous half-cycle, 5 with binary codes X (() and Yk. ( formed at inputs 13 and 134 of this cell. These operations are simultaneously carried out by comparison unit 12. At the output 19 of comparison block 12, a logical 1 signal appears if, and output 193, it appears if the inequalities Ykwt C and X |, 6 Ck. The inequalities X, Ј. C., and k- (- ki then the signal of logical 1 are present at output 19. In this case, binary codes are recorded in registers 8 and 9, all bits of which are equal to one. maximum codes, and therefore, when they arrive at the inputs of cell 1j, the contents of register 7 of this cell do not change. Thus, after two half-packs

cells 1; is recorded in the kth cycle

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The code of the jth order of the statistics of a sequence of N numbers with respect to

the numbers received from the output of the first register 2 in the (k-j) -M clock cycle on the first cell 1 drive,

Claims (1)

Claim 5 A device for extreme filtering, containing an input register and N analysis cells, where N is the filtering aetture, each analysis cell contains a comparison unit, a first register and the first switch, with the device inputs connected to the information inputs of the input register, outputs of the first group 1 -th analysis cell, where i 1,2, i .., N-1 are connected to the inputs of the first group (1 + 1) -th analysis cell, the outputs of the first group of the N-th analysis cell are outputs of the minimum number of a moving sample of the device , register synchronization inputs of all cells In each analysis, the inputs of the first and second groups are connected to the information inputs of the first and second groups of the first switch, respectively, and the inputs of the first and second groups of the comparison block, respectively, the first output of which is connected to the first control input of the first switch, the outputs of which are connected with the information inputs of the first register, the outputs of the bits of which are the outputs of the first group of this analysis cell, characterized in that, in order to enhance the functionality by bespechenii sorting numbers in sliding sample introduced therein and a block synchronization N buffer registers and to each well of analysis - second switch, the second and third registers, and outputs bit rows input register connected to the data inputs of the first register delayed 0 five 0 five 0 five 0 five The inputs of the third group of the Nth analysis cell, the bits of the 1st buffer register are connected to the information inputs (i-fl) -ro of the buffer register, the bits of the N-ro bits of the buffer register are connected to the inputs of the second group of the Nth cell analysis, the inputs of the i-th analysis cell of the second and third groups are connected to the outputs of the second and third groups respectively (1-4-1) -th analysis cell, the outputs of the first group of the i-th analysis cell are the outputs of the 1st sorted sliding number device sampling, synchronization inputs of all registers of all cells analysis connected to the first output of the synchronization unit, the second and third outputs of which are connected to the inputs of synchronization and recording resolution of all buffer registers and input register, respectively; in each analysis cell, the inputs of the second group are connected to the information inputs of the first group of the second switch, whose outputs are connected to the information inputs the second register, the inputs of the third group of analysis cells are connected to the information inputs of the third register and to the inputs of the third group of the comparison unit, the first and second The outputs of which are connected respectively to the control input of the second switch and the second control input of the first switch, the third output of the comparison unit is connected to the installation inputs to the unit state of all the bits of the second and third registers, the outputs of which bits are the outputs of the second and third groups, respectively the analysis cells, the outputs of the first register bits are connected to the information inputs of the third group of the first and second groups of the second switch, as well as with the inputs of the fourth group of the comparison block, Fig.Z J 232 " pg 21 of J 22 L. 20 Rig.C.