GB2082857A - Determining the frequency of an alternating signal - Google Patents

Abstract

A method of determining the frequency of an alternating signal in sampled form e.g. pulse code modulated or pulse amplitude modulated comprises inputing each signal sample sequentially (INA), recording the new and previous signal amplitude (RNPA), comparing the new and previous amplitudes (CNPA) to decide whether a zero crossing has occurred (FZC?), storing the signal amplitudes on either side of the first zero crossing (SNPF), inputting new signal samples (INSA), recording new and previous signal amplitudes (RNPS), incrementing a sample counter (ISC), comparing new and previous sample amplitudes (CNPS) to decide whether a zero crossing has occurred (ZC?), incrementing the zero crossing counter (IZC), deciding whether the nth zero crossing has occurred (NZC?), storing the sample amplitudes on each side of the nth zero crossing (SNPN), signalling to the calculator unit that the nth zero crossing has occurred (SNZC), reading the sample stores (RSS), reading the sample counter (RSC), and calculating the frequency (FC). The frequency may be calculated from the relationship <IMAGE> where N is the number of cycles of the alternating signal in the period between the first and nth zero crossing, Ts is the period of the signal samples, Ns is the number of sample intervals between the first and nth zero crossing, a1 is the signal amplitude immediately before the first zero crossing, a2 is the signal amplitude immediately after the first zero crossing, a3 is the signal amplitude immediately before the nth zero crossing, and a4 is the signal amplitude immediately after the nth zero crossing. Apparatus for performing the method is disclosed and its use in MF signalling receivers for telephony explained. <IMAGE>

Description

SPECIFICATION Determining the frequency of an alternating signal The invention relates to a method of an apparatus for determining the frequency of an alternating signal.

The invention may be applied to the detection of signalling tones in a telephony network. A commonly used signalling system for telephony comprises the transmission of pairs of tones one of which is selected from a high frequency group and the other from a low frequency group. In the high frequency group the frequencies are 1209Hz, 1336Hz, 1477Hz and 1633Hz while the low frequency group comprises tones at frequencies of 697Hz, 770Hz, 852Hz and 941 Hz. Selected pairs of frequencies represent the digits 0 to 9 and other pairs may represent further functions.

For analogue tone signal inputs a number of different techniques have been used to detect the frequencies of the tones. One method is to use eight filters each having a bandpass characteristic and detecting the amplitude of the signal emerging from the outputs of the filters. A second method is to measure the period of a predetermined number of cycles of the input signal. This method requiring an accurate determination of the instants of zero crossings of the input signal. A further method is to use the corelation between the input signal and each of the tones to be detected.

With a sampled tone signal input such as a pulse code modulated (PCM) or pulse amplitude modulated (PAM) signal it would be possible to replace the analogue filters of the first method with digital filters to produce a detector. Further a detector using correlation techniques is known from U.K.

Patent No. 1 566164. However with a sampled signal measurement of the period of a predetermined number of cycles of an input signal presents the problem that the instants of zero crossings cannot be accurately determined since they may fall anywhere in the intervals between the sample times. It can be shown that if a 1% discrimination between the two highest frequencies is required and the period is measured over 20 cycles then the error in determining the instants of zero crossings must be less than 10% of one cycle which is equivalent to half a sample period of an 8kHz PCM signal.

It is an object of the invention to provide a method of detrmining the frequency of an alternating signal from samples of the alternating signal taken at regular time intervals.

The inventon provides a method of determining the frequency of an alternating signal comprising the steps of: sampling the signal at regular intervals; detecting from the signal samples when a zero crossing of the signal has occurred; storing the magnitudes of the signal samples immediately before and after the first zero crossing detected; counting the number of signal samples during a period corresponding to n zero crossings of the alternating signal, where n is an integer; storing the magnitudes of the signal samples immediately before and after the nth zero crossing; linearly interpolating between the sample signals on either side of the first zero crossing to define the instant of the first zero crossing; linearly interpolating between the sample signals on either side of the nth zero crossing to define the instant of the nth zero crossing; and using the defined instants of the first and nth zero crossings to determine the frequency of the alternating signal.

By linearly interpolating between the sample signals on either side of the first and last zero crossings the instant of zero crossing may be more accurately determined. Since only the first and last zero crossings have to be accurately located only the samples on either side of these crossings have to be stored in order to calculate the frequency. An alternative approach would be to use an interpolative digital filter to increase the effective sampling frequency of the input signal. However, this is inefficient in terms of the required computing power, as is any real time interpolation technique, since it is only necessary to accurately locate the initial and final zero crossing points.

The invention further provides apparatus for determining the frequency of an alternating signal comprising means for sampling the signal at regular intervals; means for detecting from the signal samples when a zero crossing of the signal has occurred; means for storing the magnitudes of the signal samples immediately before and after the first zero crossing detected; means for counting the number of signal samples during the period corresponding to n zero crossings of the alternating signal, where n is an integer; means for storing the magnitudes of the signal samples immediately before and after the nth zero crossing; means for linearly interpolating between the sampled signals on either side of the first zero crossing to define the instant of the first zero crossing; means for linearly interpolating between the sample signals on either side of the nth zero crossing to define the instant of the nth zero crossing; and means for determining the frequency of the alternating signal using the defined instants of the first and nth zero crossings.

The apparatus may comprise means for converting the sampled signal to a pulse code modulated signal before the detection of zero crossings. The pulse code may include a bit indicating the sign of the alternating signal and the means for detecting zero crossings may comprise a coincidence detector which produces an output indicative of a zero crossing when the signs of successive signal samples are different.

The apparatus may comprise means for calculating the frequency from the formula

where N is the number of cycles of the alternating signal in the period between the first and nth zero crossing, Ts is the period of the signal samples, Ns is the number of sample intervals between the first and nth zero crossing, a 1 is the signal amplitude immediately before the first zero crossing, a2 is the signal amplitude immediately after the first zero crossing, a3 is the signal amplitude immediately before the nth zero crossing, and a4 is the signal amplitude immediately after the nth zero crossing.

The invention yet further provides a multifrequency receiver comprising a band splitting filter for separating signals having a frequency in a first band of frequency from signals having a frequency in a second band of frequencies, a first frequency detector for detecting signals having a frequency in the first band, the first frequency detector comprising apparatus as described in either of the two preceding paragraphs, a second frequency detector for detecting signals having a frequency in the second band, the second frequency detector comprising apparatus as described in either of the two preceding paragraphs, and means for producing an output signal when a signal comprising a component having a frequency in the first band and a component having a frequency in the second band is detected.

The multifrequency receiver may comprise means for determining the ratio of the peak value to the mean value of the signals applied to the first and second frequency detectors and means for inhibiting the output of the receiver if the ratio falls outside a predetermined range.

The multifrequency receiver may comprise means for determining the ratio of the peak value to the mean value of the signals applied to the first and second frequency detectors and means for inhibiting the output of the receiver if the ratio exceeds a predetermined limit.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 illustrates an input waveform and a sampled version of the input waveform, Figure 2 shows in block schematic form apparatus for determining the frequency of an input signal according to the invention, Figure 3 shows a flow chart of the steps of a method of determining the frequency of an alternating signal according to the invention, Figure 4 shows in block schematic form one embodiment of the data acquisition unit shown in Figure 2, Figure 5 shows in block schematic form a multifrequency receiver according to the invention, Figure 6 shows a mean value detector suitable for use in the multifrequency receiver shown in Figure 5 and Figure 7 shows a peak detector suitable for use in the multifrequency detector shown in Figure 5.

Figure 1 shows an alternating waveform which is sampled at intervals Ts. If the sampling periods are not synchronised with the alternating waveforms the exact positions of the zero crossings of the alternating waveform cannot be determined directly from the samples. A method used with unsampled alternating signals to determine the signal frequency is to measure the time between a specified number n of zero crossings and calculate the frequency from the relationship N f = (1) T where f is the frequency of the alternating signal, N is the number of cycles of the alternating signal between the first and nth zero crossing, and T is the time between the first and nth zero crossing. With an unsampled alternating signal the instants of the zero crossings can be accurately determined, e.g. of the order of 18 second, but with a sampled waveform there is an uncertainty which is dependent on the sampling period. Thus the accuracy with which the frequency of a sampled waveform can be determined by means of a zero-crossing detector is dependent on the sampling frequency.

A method of determining the frequency of a sampled waveform according to the invention uses zero crossing detection in which the signal samples on each side of the first and nth zero crossing are stored and used to perform a linear interpolation to more accurately define the instants of zero crossing.

Thus in order to calculate the frequency of the alternating signal from measurement of the signal samples the frequency may be derived from the relationship

where N is the number of cycles of the alternating signal in the period between the first and nth zero crossing, Ts is the period of the signal samples, Ns is the number of sample intervals between the first and nth zero crossing, a1 is the signal amplitude immediately before the first zero crossing, a2 is the signal amplitude immediately after the first zero crossing, a3 is the signal amplitude immediately before the nth zero crossing, and a4 is the signal amplitude immediately after the nth zero crossing.

It is only necessary to accurately determine the instants of the first and last zero crossings. The instants of the intermediate zero crossings are not used rather the number of such zero crossings is counted and the total determined from the denominator of relationship (2).

Figure 2 shows in block schematic form an embodiment of apparatus according to the invention for determining the frequency of a sampled an alternating signal. The apparatus comprises an input terminal 1 to which a sampled alternating signal is applied, a data acquisition unit 2, a calculator unit 3 and an output unit 4. The input signal may be of any sampled form, e.g. P.C.M. (Pulse code modulated), PAM (Pulse amplitude modulated), D.P.C.M. (Differential pulse code modulated), the data acquisition unit 2 being appropriately designed for the form of signal to. be applied. The calculator unit 3 receives data from the data acquisition unit 2 via a data bus 5 in response to address signals generated in the calculator unit 3 and fed to the data acquisition unit 2 via-an address bus 6.A start signal is fed to the data acquisition unit 2 via a terminal 7 and a signal is fed to the calculator unit 3 from the data acquisition unit 2 via a line 8 to inform the calculator that the required data has been acquired.

The data acquisition unit 2 stores the values of the sampled signals on each side of the first zero crossing after the start signal has been produced and the values of the sampled signal on each side of the nth zero crossing after the start signal has been produced. The data acquisition unit 2 also counts the number of signal samples between the first and nth zero crossing and produces a signal when the nth zero crossing has been detected which is fed via line 8 to enable the calculator unit 3. When the calculator unit 3 receives the enable signal it sends address signals to the date acquisition unit along address bus 6 to interrogate the stores and counters is the data acquisition unit 2.The contents of these stores and counters are then fed to the calculator unit via the data bus 5 and used to calculate the frequency using the relationship (2); The calculated frequency is then fed to the output unit 4 over a line 9.

The output unit 4 may take various forms. It could comprise a decimal display unit which directly displayed the frequency or alternatively the period of the alternating signal. In an alternative embodiment it could comprise a'look-up table in which the calculated frequenc'y or period is compared with preset limits and a valid or invalid signal produced as a result of the c6rnpsrisqn. In such an embodiment it is possible to construct the look-up table so that the calculator unit 3 only needs to determine the bracketed portion of the denominator of expression (2) since the number of cycled of the alternating signal over which the measurement is made and the period of the signal samples may be made a fixed constant for a given system.

Instead of making the measurements over a fixed number of cycles of the input signal it would be possible to perform the measurements over a fixed period by specifying, for example, a fixed number of samples from the first zero crossing and taking as the last or nth zero crossing the first zero crossing after the end of the fixed period. In that case the sample counter 42 (Figure 4) would preset and produce together with the zero crossing detector a data acquired signal on line 8 i.e the'fact that the counter had passed through zero would be gated with the output of the zero crnssingd'etectorto produce the data acquired signal on line 8. The number in the zero crossing counter 45 (Figure 4) would then also be presented to the calculator unit.Further by storing the sample values on teach side of every zero crossing it would be possible to use as the final zero crossing the one immediateT'y'tefore the end of the preset time. It would, of course, be necessary to at least temporarily store the number of sample periods at the latest zero crossing to enable relationship (2) to be evaluated.

Figure 3 is a flow diagram illustrating a method of determining the frequency of a sampled alternating signal according to the invention in which the apparatus shown in Figure 2 may be used. The method will be described with reference to the apparatus shown in Figure 2 but is not respected to Use with such apparatus. The functions of each of the labelled blocks in the flow diagram are summarised in Table 1.

TABLE 1 S - Start INA - Input new signal sample amplitude RNPA - Record new and previous signal sample amplitudes CNPA - Compare new and previous signal sample amplitudes FZC? - Has first zero crossing occurred? SNPF - Store signal amplitudes on each side of first zero crossIng INSA - Input new signal sample amplitude RNPS - Record new and previous signal sample amplitudes ISC - Increment sample counter CNPS - Compare new and previous signal sample amplitudes ZO? - Zero crossing detected? IZC - Increment zero crossing counter NZC? - nth zero crossing? SNPN - Store signal amplitudes on each side of nth zero crossing SNZC - Signal nth zero crossing to calculator RSS - Read sample stores RSC - Read sample counter FC - Calculate frequency E - End After a start signal is generated and applied to input 1 of the apparatus, block S on the flow diagram; the first step (INA) is to apply the sampled alternating signal to the input 1. The current sample is then temporarily stored together with the previous sample (RNPA). The present and previous samples are then compared (CNPA) and a decision taken as to whether a zero crossing has occurred (FZC?).If a zero crossing has not occurred then the steps of inputting the sample temporarily storing and comparing the present and preceding samples are repeated. When the zero crossing is detected the present and preceding samples are stored (SNPF) for subsequent manipulation.

After detection of the first zero crossing further signal samples are fed to input 1 (INw, the new and previous signal sample amplitudes are temporarily stored (RNPS), a sample- counter is incremented (ISC) as each signal sample is received, and the present and preceding samples am' compared (CNPS). A decision is then taken as a result of this comparison as to whether a zera crossing has occurred (ZC?). If the answer is NO then the steps (INS), (RNPS), (ISC) and (CNPS) are repeated. When the answer is YES the zero crossing counter is incremented (IZC) and a decision made as to whether the rrth zero crossing has been reached (NZC?). If the answer is NO then the steps (INSA), (RNPS), (ISC), (CNPS), (ZC?) and (IZC) are repeated.When the answer is YES the present and preceding samples are stored (SNPN) for subsequent manipulation. The data acquisition unit 2 then signals on line 8 to the calculator unit 3 then n zero crossings have been detected (SNZC) and that consequently the data required to determine the frequency has been acquired and is available within the data acquisition unit 2. the calculator unit 3 then addresses the data acquisition unit 2 to read the contents of the sample stores (RSS) to obtain the amplitudes of the signal samples on each side of the first and nth zero crossing, and to read the sample counter (RSC) to obtain the number of samples in the period between the first and nth zero crossing. From the information read from the data acquisition unit 2 the calculator unit 3 calculates the frequency of the input signal (FC) by use of the expression (2). The procedure then ends (E) until a further start signal (S) is generated.

Figure 4 shows in block schematic form an embodiment of the data acquisition unit 2 of Figure 2 which is suitable for a pulse code modulated (PCM) input signal.

The start signal is applied via terminal 7 and a line 70 to reset an RS bistable circuit 41, an RS bistable circuit 89, a sample counter 42, and further via an OR gate 43 an RS bistable circuit 44 and via a line 71 and a delay circuit 46 to preload a down counter 45. The input signal is fed via terminal 1 to the input of a serial to parallel converter 47, the signal being clocked into the converter by a signal applied via a terminal 48 on line 481 at the bit rate. If the signal is presented to the input 1 in parallel form then the serial to parallel converter 47 is omitted. The parallel data is clocked out of the converter 47 and into a first register 49 by a signal at the sample rate hereinafter referred to as the sample clock which is applied via a terminal 50 on line 511.The contents of the first register 49 are clocked out and into a second register 51 by the sample clock on line 502 so that the first register 49 contains the current signal sample and the second register 51 the preceding signal sample. The path 52 between the input terminal 1 and the converter 47 consists of a single conductor while the paths 53 and 54 between the converter 47 and the first register 49 and the second register 51 comprises as many conductors as there are bits in the PCM code to define the sample magnitude. A further link 55 connects a further output of register 49 to a further input of register 51 to transfer a bit which represents the polarity or sign of the sampled signal.The further output of register 49 is also connected to a first input of an AND gate 56 via a line 57 while a corresponding output of register 51 is connected to a second input of the AND gate 56 via an inverter 58. The output of the down counter 45 is connected to a third input of the AND gate 56 via a line 59 and an inverter 60. The AND gate 56 when fed with the sign and inverted sign bits from registers 49 and 51 respectively forms a zero crossing detector and applies a clock signal via a line 61 to the counter 45 when a positive going zero crossing occurs.

When the first zera crossing after the start signal is detected the output signal from AND gate 56 is applied via lines 62 and 63 to a first input of an AND gate 64 and via line 62 and delay circuit 65 to the set input of bistable circuit 41.The Q output of the bistable 41 is connected to a second input of AND gate 64. Since the start signal on terminal 7 has reset the bistable 41, the AND gate 64 is enabled and produces a signal at its output which is fed via a line 66 to an enable input on two registers 67 and 68. The data inputs of register 67 are connected via a path 69 to the data outputs of register 49 while the data inputs of register 68 are connected via a path 80 to the data outputs of register 51.The enable signal generated by AND gate 64 causes the contents of the register 49 and 51 to be read into registers 67 and 68 thus storing the samples occurring immediately before and immediately after the first positive going zero crossing after the start signal. As with paths 53 and 54 the paths 69 and 80 comprise as many conductors as there are bits in the PCM code defining the magnitude of the signal Sample.

After a period which is dependent on the delay introduced by the delay circuit 65 the bistable 41 is set and the Output now inhibits the AND gate 64 to prevent subsequent samples being transferred from the registers 49 and 51 to resgisters 67 and 68.

The output of AND gate 56 is also fed via line 81 to the set input of bistable 44 whose Q output is connected via a line 82 to a first input of an AND gate 83. The AND gate 83 has its second input connected to the sample clock signal via a line 514 and its output connected to the clock input of the sample counter 42. Thus when the first zero crossing is detected the bistable 44 is set, the AND gate 83 is enabled and subsequent sample clock pulses will increment the sample counter 42.

As each subsequent sample is presented at the input 1 the sample counter 42 is incremented, the new sample is entered in register 49 and the preceding sample transferrered to register 51. Each positive going zero crossing will produce an output from AND gate 56 which will decrement the counter 45 but will not affect the bistables 41 and 44 since they are already set. However, when the number of zero crossings detected equals the number preloaded into the counter 45 it produces an output signal which is fed via a line 84 to a first input of an AND gate 85 and via a delay circuit 90 to the set input of bistable 89. The second input of the AND gate 85 is connected to the Q output of the bistable 89 and hence AND gate 85 produces an output signal which enables to registers 86 and 87 via a line 88.The data inputs of registers 86 and 87 are connected to the data outputs of registers 49 and 51 via paths 69 and 80 respectively. Thus the contents of registers 49 and 51 are read into the registers 86 and 87 respectively. Registers 86 and 87 now hold magnitudes of the samples occurring immediately before and after the nth positive going zero crossing, when n is the number preloaded into the counter 45.

After a period which is dependent on the delay introduced by the delay circuit. 90 the bistable 89 is set and the Q output now inhibits the AND gate 85 to prevent the registers 86 and 87 following any subsequent changes in the contents of registers 49 and 51.

The output of counter 45 is also applied via line 59 and inverter 60 to the third input of AND gate 56 and thus inhibits that gate when the count in the counter reaches zero thus preventing any further signals indicative of zero crossings. Further the output of counter 45 is connected via lines 59 and 91 to a second input or OR gate 43 and causes bistable 44 to be reset and the 0 output to inhibit AND gate 83 via line 82. This prevents the sample clock on line 504 from further incrementing the counter 42.

The output of the counter 45 is available at terminal 8 and is used to signal to the calculator unit 3 (Figure 2) that the data required for the calculation of the frequency of the input signal has been acquired and is available. The calculator unit 3 then addresses the counter 42 and the registers 67, 68, 86, 87 in turn via terminal 91 on path 6 and receives the information along path 6 via terminal 92. The path 6 may have five individual conductors or may be a three way bus with the counter and registers being addressed by a binary code. The path 5 will have as many conductors as there are bits stored in the registers or the maximum number of bits of the counter 42.

Four a pulse amplitude modulated signal the registers 49,51,67,68,86,87 could be replaced by sample and hold circuits which would store analogue representations of the pulse amplitudes. If a digital calculating unit was used it would, of course be necessary to include an analogue to digital converter in the path between the sample and hold circuits and the calculating unit. A different form of zero crossing detector would be required and could, for example, be constructed from differential amplifiers which detect whether the voltages stored in the sample and hold circuits are above or below a preset threshold value.

A differential pulse code modulated signal would be fed to an accumulator and a change in sign of the accumulated signal would indicate a zero crossing. The value accumulated on either side of the first and nth zero crossing could be fed to registers 67, 68, 86 and 87 for subsequent calculation.

Figure 5 shows a multifrequency signalling receiver which is capable of operating on sampled alternating signals. The receiver is for an MF4 signalling system which comprises combinations of two tones, one in a high frequency band and the other in a low frequency band, each tone being selected from a group of four tones. Such signalling systems are used in telephony and receivers for non sampled alternating input signals are readily available from several manufacturers.

The receiver shown in Figure 5 comprises an input terminal 501 by means of which a composite sampled signal is fed to a digital band splitting filter 502 which produces a first output on line 503 in a high band of frequencies and a second output on line 504 in a low band of frequencies from the composite signal. The signal on line 503 is fed to a first date acquisition unit 505 and thence to a first -calculator unit 506. The signal on line 504 is similarly fed to a second data acquisition unit 507 and second calculator 508. The outputs of calculators 506 and 508 are fed to an output unit 509 and output terminal 510.The first data acquisition unit 505 and first calculator 506 together with the output unit 509 form a first detector for determining the frequency of the signal in the high frequency band while the second data acquisition unit 507, second calculator unit 508 and the output unit 509 from a second detector for determining the frequency of the signal in the low frequency band. The first and second detectors for determining the frequency of the input signal are of the form described with reference to Figures 1 to 4 of the accompanying drawings. The form of the output unit 509 will depend on the application in which the receiver is used and may be designed to produce an output in several forms, e.g. loop disconnect pulses or binary codes.The calculator units 506 and 508 may take the form of a microprocessor and if a sufficiently fast device is chosen one microprocessor may service both the data acquisition units. With a pulse code modulated input the data acquisition units may be combined with the calculator unit, the stores for the sampled values being formed by registers within the calculator unit.

The output unit 509 may include a look up table which may contain representations of the limits of the periods for n cycles of each of the signalling tones to be detected. In that case only the denominator of relationship (2) need be determined. The time so determined is compared with the values stored in the look up table to see whether it falls within the limits stored in the look up table. If so then the output unit 509 produces an output to indicate that a desired tone is present.

The receiver described with reference to Figure 5 will produce an output to indicate when appropriate signalling tones have been received but may also produce false outputs in response to speech signals. In order to reduce the likelihood of such false outputs being produced the peak and mean levels of the signals on lines 503 and 504 may be measured, the ratio of the peak to the mean level determined, and if this ratio exceeds a preset limit the output of the receiver inhibited. It is known from U.K. Patent No. 381940 that it is possible to distinguish between sinusoidal waveforms and speech waveforms by determining'the ratio of the peak to the mean value of the signal, this ratio being greater for speech signals than for sinusoidal signals.Tests have shown that for all eight MF4 tones, i.e. the tones designated in the second paragraph, the peak to mean ratio lies within the range 1.50 to 1.61 over the dynamic range of the receiver specified by the British Post Office when calculated over twenty cycles of the input signal. As the number of cycles of input frequency is increased the ratio approaches more closely to the theoretical value for a sinewave.

Figures 6 and 7 show arrangements for determining the mean value and the peak value of PCM input signals. The arrangement shown in Figure 6 comprises an input terminal 601 through which the input signal is fed to an adder 602 via a path 611. A clock signal at the sample rate is fed via a terminal 603 to the clock input of a counter 604 via a line 612 and to an enable input of a register 605 via a line 61 3 to read the output of the adder 602 into the register 605 via a path 614. The output of the register 605 is fed to a second input of the adder 602 via a path 61 5 and thus the output of the adder 602 comprises the sum of the current sample and the contents of register 605. This output is clocked into register 605 by the next sample clock pulse on terminal 603 and thus register 605 will contain the sum of all the samples. The counter 604 is clocked on every sample clock pulse and hence the sum contained in the register 605 divided by the count of counter 604 will be representative of the mean value of the waveform. A reset pulse may be applied to the counter 604 and register 605 via a terminal 606 and lines 616 and 617. The contents of the counter 604 and register 605 may be read by the calculator unit by means of address signals via terminal 607 and lines 618 and 61 9 and data lines 608 through terminal 609. The reset pulse on terminal 606 may be the same signal as that applied via terminal 7 to the data acquisition unit 2 (Figure 4). The clock signal on terminal 603 should be inhibited by the calculator enable signal produced at terminal 8 of the data acquisition unit (Figure 4).When the PCM signal comprises a number of bits defining the sample magnitude plus a sign bit only the sample magnitude bits are applied to the adder and thus the mean is automatically obtained by merely dividing the accumulated sample magnitudes by the number of samples.

The arrangement shown in Figure 7 for detecting the peak value of the input signal comprises a terminal 701 by which a PCM input signal is applied via paths 721 and 722 to a first input of a first comparator 702 and a second comparator 703 and via paths 723 and 724 to inputs of a first register 704 and a second register 705. It is assumed in this embodiment that the PCM input is an 8 bit parallel code and that comparator 702 operates on the four most significant bits and the comparator 703 operates on the four least significant bits. Hence paths 721,722,723 and 724 will comprise four conductors. The registers 704 and 705 also hold four bits each, register 704 being allocated to the most significant bits.The outputs of register 704 are connected to a second input of comparator 702 via a path 725 and the outputs of register 705 are connected to a second input of comparator 703 via a path 726.

The comparator 702 has a first output 706 which indicates whether the value of the four most significant bits of the input signal is greater than the value stored in register 704. This output is fed through an OR gate 707 and an AND gate 708 to an enable input of registers 704 and 705 to cause the input signal to be read is to the registers 704 and 705 if the four most significant bits of the input signal are greater than the four bits currently stored in register 704. The second input of AND gate 708 is connected via a line 729 to a terminal 709 through which the sample clock is applied to determine the time of transfer of the input signal into the registers 704 and 705.

The comparator 703 has an output 710 which indicates whether the value of the four least significant bits of the input signal is greater than the value stored in register 705 and this is fed together with a second output 711 of the comparator 702 to the inputs of an AND gate 712. The second output 711 of comparator 702 produces a signal to enable AND gate 712 when the value of the four most significant bits of the input signal is equal to the value stored in register 704. The output of AND gate 712 is fed via the second input of OR gate 707 and AND gate 708 to enable the register 704 and 705 so that the input signal is transferred to the registers 704 and 705 when the sample clock is applied.

Thus the registers 704 and 705 will store the peak value of the signal since the AND gate 708 will only enable the input signal to be read into the registers when it is greater than the value already stored. A reset signal, which may be the start signal applied to terminal 7 of the data acquisition unit 2 (Figure 4), is applied to the registers 704 and 705 via a terminal 713 and lines 727 and 728 respecteively to set the register 704 and 705 to zero at the start of each measurement cycle. The clock signal on terminal 709 should be inhibited when the data acquisition unit 2 signals to the calculator that the data has been acquired i.e. when the nth zero crossing is detected. The calculator then addresses the registers 704 and 705 via terminal 714 and lines 730 and 731 and receives the data from the registers via paths 732, 733 and terminal 715.Paths 732 and 733 both comprise four conductors.

While the frequency detector will detect the presence of tones represented by companded PCM codes when such codes are used it would not be possible to provide protection against the false detection of speech as the presence of tones by measuring the peak to mean ratio of the signal. In this case a different method of providing speech immunity would be necessary. This could be achieved, for example, by measuring the instant of each zero crossing and since speech will cause jitter in the instants of zero crossings, detecting whether such jitter exists and inhibiting the output of the receiver when jitter is detected.

Alternatively the compressed PCM code may be expanded to form a linear PCM code before application to the frequency detector. When a digital filter is used it will be necessary to linearise the PCM signal to perform at least some of the required calculations though the product terms may be obtained directly from the logarithmically compressed PCM signal.

Further the compressed PCM code could be linearised before being applied to the mean detector this linearisation being achieved by means of decoding logic or by means of shift registers. The linearised code could be stored in a read only memory (ROM) addressed by the compressed code.

It has been found that when an eight bit logarithmically compressed code is expanded to a linear fourteen bit code the frequency detector will operate satisfactory using the nine most significant bits, the most significant bit being used as a sign bit. Consequently in the embodiment of the data acquisition unit 2 shown in Figure 4 the paths 53, 69 and 80 will comprise eight conductors and the registers 49, 51, 67, 68, 86 and 87 will each be capable of storing eight bits. The path 5 will comprise at least eight conductors, the total number being dependent on the maximum total count of the sample counter 42.

Claims (14)

1. A method of determining the frequency of an alternating signal comprising the steps of: sampling the signal at regular intervals; detecting from the signal samples when a zero crossing of the signal has occurred; storing the magnitudes of the signal samples immediately before and after the first zero crossing detected; counting the number of signal samples during a period corresponding to n zero crossings of the alternating signal, where n is an integer; storing the magnitudes of the signal samples immediately before and after the nth zero crossing; linearly interpolating between the sampled signals on either side of the first zero crossing to define the instant of the first zero crossing; linearly interpolating between the sample signals on either side of the nth zero crossing to define the instant of the nth zero crossing; and using the defined instants of the first and nth zero crossings to determine the frequency of the alternating signal.

2. A method according to Claim 1 comprising the step of converting the sampled signal to a pulse code modulated signal before the detection of zero crossings.

3. A method according to Claims 1 or 2 in which the zero crossings in one direction only are detected.

4. A method according to any of Claims 1 to 3 comprising the step of calculating the frequency of the formula

where N is the number of cycles of the alternating signal in the period between the first and nth zero crossing, Ts is the period of the signal samples, Ns is the number of sample intervals between the first and nth zero crossing, al is the signal amplitude immediately before the first zero crossing, a2 is the signal amplitude immediately after the first zero crossing, a3 is the signal amplitude immediately before the nth zero crossing, and a4 is the signal amplitude immediately after the nth zero crossing.

5. A method of determining the frequency of an alternating signal substantially as described herein with reference to the accompanying drawings.

6. Apparatus for determining the frequency of an alternating signal comprising means for sampling the signal at regular intervals; means for detecting from the signal samples when a zero crossing of the signal has occurred; means for storing the magnitudes of the signal samples immediately before and after the zero crossing detected; means for counting the number of signal samples during a period corresponding to n zero crossings of the alternating signal, where n is an integer; means for storing the magnitudes of the signal samples immediately before and after the nth zero crossing; means for linearly interpolating between the sampled signals on either side of the first zero crossing to define the instant of the first zero crossing; means for linearly interpolating between the sample signals on either side of the nth zero crossing to define the isntant of the nth zero crossing; and means for determining the frequency of the alternating signal using the defined instants of the first and nth zero crossings.

7. Apparatus as claimed in Claim 6 comprising means for converting the sampled signal to a pulse code modulated signal before the detection of zero crossings.

8. Apparatus as claimed in Claims 6 or 7 in which the zero crossings in one direction only are detected.

9. Apparatus as claimed in any of Claims 6 to 8 comprising means for calculating the frequency from the formula

where N is the number of cycles of the alternating signal in the period between the first and nth zero crossing, Ts is the period of the signal samples, Ns is the number of sample intervals between the first and nth zero crossing, a1 is the signal amplitude immediately before the first zero crossing, a2 is the signal amplitude immediately after the first zero crossing, a3 is the signal amplitude immediately before the nth zero crossing, and a4 is the signal amplitude immediately after the nth zero crossing.

1 0. Apparatus as claimed in Claim 7 in which the pulse code include a bit indicating the sign of the alternating signal and the means for detecting zero crossings comprises a coincidence detector which produces an output indicative of a zero crossing when the signs of successive signal samples are different.

11. Apparatus for determining the frequency of an alternating signal substantially as described herein with reference to Figures 1 to 3 or to Figures 1 to 4 of the accompanying drawings.

1 2. A multifrequency receiver comprising a band splitting filter for separating signals having a frequency in a first band of frequency from signals having a frequency in a second band of frequencies, a first frequency detector for detecting signals having a frequency in the first band, the first frequency detector comprising apparatus as claimed in any of Claims 6 to 11, a second frequency detector for detecting signals having a frequency in the second band, the second frequency detector comprising apparatus as claimed in any of Claims 6 to 11, and means for producing an output signal when a signal comprising a component having a frequency in the first band and a component having a frequency in the second band is detected.

13. A multifrequency receiver as claimed in Claim 12 comprising means for determining the ratio of the peak value to the mean value of the signals applied to the first and second frequency detectors and means for inhibiting the output of the receiver if the ratio falls outside a predetermined range.

14. A multifrequency receiver as claimed in Claim 12 comprising means for determining the ratio of the peak value to the mean value of the signals applied to the first and second frequency detectors and means for inhibiting the output of the receiver if the ratio exceeds a predetermined limited.

1 5. A multifrequency receiver substantially as described herein with reference to Figure 5 or to Figures 5 to 7 of the accompanying drawings.