SU1298719A1 - Device for collecting flaw detection information - Google Patents

Abstract

The invention relates to the collection and processing of flaw detection information in non-destructive testing installations and may not be used for automatic ultrasonic testing of extended products. The purpose of the invention is to improve the accuracy of control. The device allows to increase productivity while maintaining a high level of reliability of control when using the S 20 II Srig1 Research Institute of the computer system for automatic calculation of coordinates, types and parameters of defects. The device frees the processor of the computing system from the function of entering flaw detection data by quickly loading the flaw detection information into one of the two memory blocks, while the second memory block is connected to the address, data and control buses of the processor of the computing system that processes flaw detection data previously accumulated in the corresponding memory block. The device contains a measuring unit 1, the first 2 and second 3 pulse counters, the first 4 and second 5 j registers, the first 6 and second 7 blocks. memory, first 8 and second 9 switches, first 10 demultiplexer, first element OR 11, pulse distributor 12, third 13 pulse counter, multiplexer 14, second 15 demultiplexer, fourth 16 pulse counter, second element OR 17, counting trigger 18. 5 silt .. cl

Description

1-12

The invention relates to non-destructive testing and can be used in ultrasonic flaw detection scanning systems containing a computing device for determining types, sizes and. defect coordinates

The purpose of the invention is to make the control accurate.

Figure 1 shows the block diagram of the device} in Fig, 2 is a diagram of a pulse distributor; on fig.Z - diagram of the measuring unit; FIG. 4 is a switch diagram for one bit; FIG. 3 is a demultiplexer circuit for one bit.

The device (figure 1) contains the measuring unit 1, the first counter of 2 pulses (longitudinal coordinate counter), the second counter of 3 pulses (counter transverse coordinate), the first register 4 (three-stable data buffer), the second register 5 (three-stable data buffer) , the first 6 and second 7 memory blocks, the first switch 8 (address switch), the second switch 9 (write switch), the first demultiplexer, 1 O, the first element. OR 11, pulse distributor 12, third pulse counter 13 pulse multiplexer 14, second demultiplexer 15, fourth pulse counter 16 (address counter), second IL 17, counting trigger 18, control bus 19, bus 20 a, dragging, information bus 21 .

The distributor 12 pulses, (figure 2) contains the multivibrator 22, the element And 23, the counter 24 pulses, the decoder 25, the RS-trigger 26.

Measuring unit 1 (FIG. 3) contains measuring channels 21-21, each of which consists of comparator 28, threshold voltage source 29, RS flip-flop 30, And 31 element, analog-digital converter 32, register 33, and peak detector 34

Switches 8 and 9 (FIG. 4) in each bit contain two first elements OR 35 and 35.25 four elements AND 36 and 36 g, 36 and 36 and two second elements OR 37, and 37 ,; .

Demultiplexers 10 and 15 (FIG. 5) contain in each section an element OR 38, the first 39 and the second 40 elements I.

19 2

The device for collecting flaw detection information works as follows.

Scanner transducers (not shown) move along the surface of the test item. The counters 2 of the longitudinal and 3 transverse coordinates fix, with a discreteness of lH, the longitudinal coordinate and with a resolution of 3Y, the transverse coordinate of the primary transducer of the first channel. The primary converters of the other channels are located at a known distance (in two coordinates) from the first primary converter: 1,; one-. where i 2,3, ..., N is the channel number.

If (X, Y,) are the coordinates of the first primary converter, then the coordinates of the other converters can be easily obtained using the formulas

X X, - 1.;

(, 3, ... N)

U. - lyi

The multichannel flaw detector synchronizer generates with a certain frequency probing signals arriving at the primary transducers, which convert them into ultrasonic pulses arriving through an immersion medium into a controlled product. If there is a defect, the primary transducer receives a reflected echo signal and an echo pulse is generated at the corresponding output of the multichannel flaw detector. As we approach the defect, a packet of probing signals will be generated and, accordingly, a packet of echo pulses will be received. Thus, the packets of the echo pulses with a frequency equal to the sounding frequency arrive at the input of the measuring unit 1. The amplitude of the incoming echo pulse is memorized by the peak detector 34 and compared in parallel with the comparator 28 with the threshold value Ur ,.

If the amplitude of the echo pulse exceeds the value of U, then the comparator 28 sets the RS flip-flop 30 to one state. In this state, trigger 30 permits the passage of a signal through element 31. The synchronizer of a multichannel flaw detector, with a certain delay in relation to the probing signal, generates

the sync pulse signaling the arrival of an echo and 4 pylas, the sync pulse arrives at the sync input of a measurable 1 block and switches on the analog-digital unit through element 31. a transmitter (A / D converter) 32 and zeroing register 33. A / D converter 32 converts the amplitude value of an echo pulse stored on a peak detector 34 into a digital code. Upon completion of the conversion, fo CPU 32 generates a pulse. Conversion end, which records the amplitude of the echo pulse to register 33, the peak detector f5 34 is reset and the trigger 30 is set to the zero state. The Pulse End of Conversion is the End of Measurement signal, issued by the measuring unit) 1. If an echo pulse is on which-20 channel is missing or its value is less than the U value, then the trigger 30 remains in the zero state and the sync pulse does not pass on the A / D converter 32. As a result, the A / D converter 32 does not work, and in the register 33 it is set to zero code. So, after the appearance of the clock pulse and the end of the conversion of the A / D converter 32, the output registers 33 will either have a digital code for the amplitude of the echo pulse received from this channel, or a zero code.

Data input from the output registers 33 of the measuring unit 1 and the counters 2 and 3 to the blocks 6 and 7 of the memory occurs as follows.

The state of the counting trigger 18 sets a certain switching of the inputs and outputs of blocks 4, 5, 8, 9, 10, 15. For the sake of definiteness, we assume that the counting trigger 18 is in the zero state. In this case, the output of memory block 6 through register 4 (a three-state data buffer) is connected to the data bus of the computing system 45 (buffer 4 is open). The first output of the multiplexer 15 is blocked and a zero code is output to the input of memory block 6. The switch 8 connects the bus 20 of the address of the computing system to the administrative input of the memory block 6, and the switch 9 supplies the output of the Record from the control system bus 19 to the input of the record of the memory block 6. The first output of the demultiplexer 10 sub-55 switches the output of the read bus 19 of the computer system control to the input Read block 6 of the memory. In turn, the output of memory block 7 is disabled.

register 5 (three-stable buffer {data) from the information bus 21 of the computer system (output of buffer 5 is in a high-impedance state). The second output of the demultiplexer 15 connects the output of the multiplexer 14 to the input of the memory block 7. The address switch 8 connects the output of the counter 16 to the address input of the memory block 7, and from the switch 9 supplies the second output of the distributor 12 to the input of the memory block 7. The second output of the demultiplexer 10 is blocked and gives zero potential to the input. Reading of the memory block 7.

The switching description shows that the zero state of the counting trigger 18 allows the computer system to exchange information from memory block 6, while information from measurement block 1 is written to memory block 7. Consider this process in more detail.

If at least one channel triggered the A / D converter 32 of the measuring unit 1, then the pulse End of the measurement across the first element OR 11 is fed to the trigger input of the distributor 12 pulses. As a result, the trigger 26 is set to one and allows the clock pulses from the multivibrator 21 to pass through the AND 23 element to the input of the counter 24. The counter 24 has four states: zero - the initial state, state 1, in which the counter 13 grows, state 2, which the signal 9 is sent to block 7 of the memory of the comm switch; state 3, which the counter 16 grows through. Counter 24, receiving clocked pulses, passes all these states successively, the decoder decrypts them and a sequence of pulses appears at its exits.

The first pulse changes by one the state of the counter 13, which controls the multiplexer 14. Each state of the counter 13 switches a certain input of the multiplexer 14 to the output. As a result, the information from the measuring unit 1 or the counters 2 and 3 through the multiplexer 14 and the multiplexer 15 is fed to the input of the memory unit 7. The second pulse from the pulse distributor 12 is the Write signal for memory block 7

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The contents of the address counter 16 are connected via the switch 8 to the address input of the memory block 7. The address stored in the counter 16 records the information received at the input of the memory block 7. The third pulse from the distributor 12 pulses increases the contents of the counter 16 by one, thereby preparing the next entry address. Counter 2 returns to zero status. The write cycle is over. The number of write cycles is counted by counter 13 and is equal to N + 2, where N is the number of channels in measuring unit 1. In the first and second recording cycle, the contents of counters 2 and 3 are entered into memory unit 7. Next, in each subsequent cycle input information from the next - output register 33 of the measuring unit 1.

Thus, if at least one ADC 32 of the measuring unit 1 has been triggered by the arrival of the sync pulse from the multichannel flaw detector, then the following array D will be written to the memory:

- 1 - longitudinal coordinate;

- 2 - transverse coordinate;

-.3 - the code of the amplitude of the echo pulse or the zero code (1 channel);

- D - code of the amplitude of the echo pulse or zero code (2 channel) f

and -N + 2 - the code of the amplitude of the echo pulse is N + 2.V. / y,

Ca or zero code (, N channel).

Note that the presence of a zero code indicates that this channel has not received an echo pulse.

The information is entered into the memory block 7 by the specified arrays until the counter 16 overflows. In this case, the counter 16 goes to the initial state and generates an overflow signal, which through the second element OR 17 changes the state of the counting trigger 18. Countable the trigger, being in the single state, re-switches the inputs and outputs of blocks 4, 5., 8, 9, 10 and 15 in such a way that now the memory block 7 is connected to the information bus 21 by the bus 20 of the address and

50

five

0

five

five

P

with

0

19: 6

The BUS 19 controls the computing system, and the memory block 6 is connected through the appropriate blocks to the IMM-RITUAL block 1, the counter 16, the counters 2 and 3, the distributor 12 pulses. The described data entry process will now be performed in memory block 6.

While flaw detection information is entered into memory block 6, the computer system reads the accumulated data from memory block 7 and processes them. At the same time, the process of inputting and reading out the flaw detection data can proceed in parallel, since the inputs, outputs, and control signals of both memory blocks 6 and 7 are expanded by blocks 4, 5, 8, 9, 10, and 15. Consider the process of reading data from the blocks 6 and 7 memory computing system. Let us assume, for definiteness, that the reading occurs from memory block 7, i.e. counting trigger 18 is in a single state.

The cell address of the memory block 7 from the address bus 20 through the switch 8 is fed to the address input of the memory block 7. The read signal from the control bus 19 through the second output of the demultiplexer 10 is fed to the input of the memory block 7, while the first output of the demultiplexer 10 causes the zero potential of the read input of the memory block 6. As a result, from the output of memory block 7, information through an open register 5 enters the data bus and is fixed by the processor of the computing system, while register 4 is in a high-impedance state and disconnects the output of memory block 6 from the information bus 2 of data. After reading the information from the memory block 7, the processor of the computing system embraces this cell. In this case, the signal Record from the control bus 19 through the switch 9 is fed to the input Record of the memory block 7. The zero code is recorded from the second output of the demultiplexer 15, which is blocked in this state of the counting trigger 18 (Fig. 5). Thus, after reading all the information from the storage device, it becomes zero. This circumstance and the structure of the recorded arrays D allows the processor of the computer system to easily distinguish between those recorded in the memory,

712

information The processor begins to read information from the zero cell.

If the contents of the first cell are not zero, then this is the longitudinal coordinate, the next cell contains the transverse coordinate. The following N cells contain information about the amplitude codes of the echo signals received from each channel. The sequence number of the cell counted from the cell containing the transverse coordinate indicates the channel number. If the content of any of these cells is zero, it means that the data

channels did not receive echo pulses. The following N + 2 storage cells contain a new D array and so on. Splitting is performed either up to the final address of the memory block or until the first cell of the next array is zero. This means that the processor counted and processed all flaw detection information in this block of media.

The switching of blocks 6 and 7 of memory from the buses of the computing system g i to the measuring unit 1 and the counters 2 and 3 is carried out by the counting trigger 18 according to the overflow signals of the counter 16 (this case is described above), the Start control signal and the End control signal. When turned on, the counting trigger 18 may be in an arbitrary state and connect memory block 6 or memory block 7 to the buses of the computing system. Assume that the memory block 6 is connected to the tires of the computing system. Computer processor when

. The memory inserts this memory block. Signal Start of control through the second element OR 17 transfers the counting trigger 18 to another state, as a result of which memory block 7 is connected to the buses of the computing system while zeroed memory block 6 is connected to measuring unit 1 and counters 2 and 3 and is ready to receive flaw detection information.

The processor of the computing system, using the start control signal, zeroes another memory block (in this case, memory block 7) and begins to poll its first cell. Since memory block 7 has just been reset, the process25

987

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20 L) 35 40

45 50 198

The tracer will read from the first cell a zero code signaling to him that the information has not yet been received for processing. Once the memory block 6 is full, i.e. the address counter 16 overflows, this memory block will be connected to the computer system buses, and the zero memory block 7 will overflow to the measuring unit 1 and the counters 2 and 3. The processor of the computing system will once again turn to the first cell of the memory device, this time it will be . the first cell of memory block 6 containing a non-zero longitudinal coordinate.

A read non-zero code signals the processor that the flaw-detection information has arrived for processing. The processor begins processing the incoming data, forming as already described, the arrays D. The processing program may include determining the types, coordinates and sizes of defects. While data is being processed from memory block 6, information from measuring block 1 and counters 2 and 3 is sent to zeroed memory block 7. At the same time, blocks 6 and 7 of memory for the processor of the computing system are indistinguishable from each other. After finishing flaw detection data processing and resetting the memory block (in this case, memory block 6), the processor proceeds to poll its first cell and will read zeroes from there until the memory blocks switch, i.e. in this case, until memory block 7 is connected to the system buses. The described process will continue until the signal arrives. End of control. This signal causes the next switching of blocks 6 and 7 of memory. As a result, the memory unit, partially filled with flaw detection information, is connected to the buses of the computing system, the processor processes this data and stops.

Volumes of blocks 6 and 7 of memory should be determined, based on the condition of the almost complete elimination of loss of flaw detection data (i.e. the probability of loss of flaw detection signals must be quite low - 10). Actually, this means that the processing time of the defect is .912

The copy data stored in the memory block 7 with the capacity of M bytes should almost always be less than the accumulation time of the flaw detection data in the memory block of the same volume. In general, the volume of the memory block depends on the number of channels, the statistical characteristics of the arrival intervals of the flaw detection signals on each channel and the processing time of these signals.

The proposed device does not require the processor of the computing system to enter the codes of the amplitudes of the echo pulses and their coordinates; the processor, when used with this device, is occupied only with the processing of flaw detection data. Improving the reliability of monitoring by increasing the number of channels, the use of computer systems that conduct comprehensive accounting and processing of all flaw detection information significantly reduces the performance of the monitoring. The device allows fast loading of flaw detection data, without distracting the computational tools to this procedure.

system, which allows to achieve high performance control

a given level of confidence control.

Claims (1)

Invention Formula A flaw detection information collection device containing the first memory block, the measuring block connected by the information inputs to the information inputs of the device, and the synchronous input to the first synchronization of the device, as well as the first and second pulse counters associated with the counting inputs of the second and third synchronization inputs of the device, which are distinguished by the fact that, in order to increase the control accuracy, two registers, a second memory block, a multiplexer, two demultiplexers, a counting trigger, two elements are entered and OR, the third and fourth pulse counters, two switches and a pulse distributor connected by the Start input with the output of the first element OR, the Stop input with the first output 9 10 the third pulse output, the first output with the counting input of the third pulse counter, the second output with the first control input of the second switch, and the third output with the counting input of the fourth pulse counter connected, with the first information output to the first information input of the first switch, and the second information output to the first output of the second HJM element connected by the second and third inputs respectively to the Start control and End control of the device, and the output to the counting trigger input a generator connected by an inverse output with a control input of the second register, and a direct output with control inputs of the first and second demultiplexer, with a second control input of the second switch, with a control input of the first register and with a second {1m control input of the first switch connected by the second information input with the device address width, and the first and second outputs, respectively, with the address inputs of the first and second memory blocks connected by the outputs, respectively, to the information inputs of the first and second p Registries connected to the information bus of the device connected by the control bus to the information input of the second switch and with the information input of the first demultiplexer connected to the first and second outputs are connected to the inputs of the first and second memory blocks, respectively. inputs Record respectively with the first and second outputs of the second switch, and information inputs - respectively with the first and second outputs of the second demultiplexer connected by the information input to the output multi The corresponding information inputs are connected to the output of the first pulse counter, the output of the second pulse counter and the information outputs of the measuring unit connected to the outputs of the measurement cell with the corresponding inputs of the first OR element. Out  konen measured Informal 8lod1 2 You) (0d insurance)  The end of the evening - bykpa N nor l. BUT Synchronous figz Indhr Jetsiannyi IN 0 and. 39 Ji and-a .but Editor N.Egorova Compiled by N.Gorbunova Tehred M. Khodanych Proofreader E. Roshko Order 888/50 Circulation 864 Subscription VNSh-SHI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 n i Jk FI.5