SU1112364A1 - Pulse-frequency multiplying-dividing device - Google Patents

Abstract

THE FREQUENCY-PULSE MNO "THE INDIVIDUALLY-PERFORMING DEVICE VO, containing the first and second counters, delay element, register, comparison unit, the first group of information inputs of which are connected respectively to the information outputs of the register, the information inputs of which are connected respectively to the outputs of the first counter, which zero input through the delay element is connected to the first information input of the device, the register entry input, the counting input of the first counter is connected to the second information input of the device In fact, the third information input device of the device is connected to the counting input of the second counter, the output of which is connected to its recording input, characterized in that, in order to show its accuracy by excluding dynamic errors, a key and a third counter are entered into it, the outputs of which are connected respectively to information inputs of the second counter, the input of the record of the third counter is connected to the first information input of the device, and the counting input of the third counter is connected to the output of the key (the first input of which is connected the second information input of the device, the second input of the key is connected to the output of the delay element, and the third input of the key is connected to the output of the comparison unit, the second group of inputs of which is connected to the corresponding outputs of the first counter and information: And the inputs of the third counter, and the output of the second counter inE) formational output of the device.

Description

The invention relates to automation and computer technology and is intended to perform multiplying-dividing operations on frequency signals. Devices are known that organize multiplying-dividing operations by transmitting frequency pulses F to the output for periods of time that are multiples of the second frequency F2 and repeating His frequency is with the frequency of the third signal, as a result of which the average value at the output of the device is t 1. ib,. (1) r L 1 t F2 The device consists of the first and second frequency dividers, the first and second triggers, and the first, second, and third elements AND, interconnected in an appropriate way. The main disadvantage of such devices is a significant frequency fluctuation device output. The closest in technical essence to the present invention is a multiplying-dividing device, comprising a first and second counters, a frequency divider, a transfer pulse shaping unit, a valve, a group of elements AND, a register, a delay element, and an equation block connected along the first group of information inputs the first counter, and the second group of information inputs with the outputs of the register bits, the inputs of which are connected to the outputs of the elements of the AND group, the first inputs of which are connected to the outputs of the bits of the second the second inputs of the AND elements of the group are combined and connected to the output of the transfer pulse generator and the input of the delay element, the output of which is connected to the reset input of the second counter, the counting input of which is connected to the first output of the valve, the second output of which is connected to the input of the transfer pulse former, the first valve inlet is connected to the first information input of the device through the frequency driver, the second valve inlet is connected to the second information input of the device, the third information input connects ene with a countable input of the first counter, whose reset input is connected to the output of matching unit, integrated with the control input of the transfer pulses 2j and output device. This device realizes the dependence (1). Its disadvantage is the increase in error when decreasing the ratio of frequencies RZ / 1 when changes of a small period T with a large delay are monitored at the output due to a large perioLL. T2 .. The purpose of the invention is to increase the speed and the accuracy of the operations performed by the frequency-pulse multiplier-dividing device due to the exclusion of dynamic errors. The goal is achieved by the fact that in the multiplier-separating device, containing the first and second counters, the delay element, the register and the comparison unit, the first group of information inputs of which are connected respectively to the informational ones. the register outputs, to the information inputs of which the outputs of the first counter are connected respectively, the zero input of which is connected to the first information input of the device through the delay element, the register recording input, the counting input of the first counter is connected to the second information input of the device, the third information input of the device is connected to the counting input of the second the counter, the output of which is connected to its recording input, a key and a third counter are entered, the outputs of which are connected respectively to the information input A second counter, a third counter input input with the first information input of the device, and a third counter count input connected to the output of the key, the first input of which is connected to the second information input of the device, the second input of the key connected to the output of the delay element, and the third input of the key connected to the code a comparison unit, the second group of inputs of which is connected to the corresponding codes of the first counter and the information inputs of the third counter, the output of the second counter-; The chick is an information output device. 3 The drawing shows the structures on the scheme of the frequency-pulse multiplier-dividing device. The pulse-frequency multiplying device contains the first counter 1, the second counter 2, the delay element 3, the register 5, the third counter 6, and block 7 as compared to (codes). The device works as follows. Pulses with a frequency F from the first information input of the device are sent to the control inputs of memory register 4, the third counter 6 and, through delay element 3, to the prohibiting input of key 5 and the reset input to zero of the first counter 1. At the next occurrence (i -ro) of the pulse at the first information input on the first counter 1, the code of the number N is formed. (i) the pulses of the clock RL, arriving at the second information input of the device. The code of the number NJ (i) is fed to the information inputs of the register 4 and the third counter 6, as well as to the second group of inputs of the code comparison block. At the moment of occurrence of a pulse, the code of the number N (i) is recorded in the last information input at the control inputs of register 4 and the third counter 6. The same pulse through the delay element 3 acts on the reset input of the counter 1, wrapped it in and also on the prohibition of the input of the key 5, locking the latter. After the pulse disappears at the first information input, the next one begins (the pulse frequency frequency F (. These periods determine the cycle of the multiplication-division operation. During the next period (- 1) T / s at the clock time, 2, ... The first counter 1 is formed of a linearly increasing signal. The code of the number N (i) recorded in the previous period in the third counter 6 arrives at the information inputs of the second counter 2 operating in the subtraction mode. The third information input of the device from the frequencies Fa. At the moment of zeroing of the second counter 2, a pulse is formed at its output, arriving at the output of the device and at the input to the second counter 2 of the number N. (. After writing the number N, the second counter 2 reads the frequency pulses from it Gl until the counter is zeroed out. Thus, the number N (i) Iiiil - b-, “n 1 -p (about accumulated in the previous period TD) in the first counter 1, in the subsequent period will be the formation of the period of the output stream in the second counter 2 : PL. 2 RZ This means that the frequency F. at the output of the device is equal to m. This value of the frequency P keeps c in the (i + 1) -M period of the frequency F as long as condition 4 is met (N, (i,, ( 5) and as soon as tf (t) Nai coincides, (6) then, from the output of the code comparison unit 7, the enabling signal arrives at the input of the key 5. The last signal opens and transmits the frequency T pulses to the input of the third counter 6 until the appearance of ) -ro of the frequency pulse F. Thus, in the time interval between the moments .CijHt N i + O, the counter 6 performs linear interpolation of the control signal according to the ont 4t) - F, t, If in this interval the second counter 2 is zeroed, then the number ((i) closer to N, (i + 1) than N (i) will be rewritten in it. Thus, in the indicated interval The linear interpolation of the frequency of equality is reached, (-1), i.e. when the pulse arrives at the first information input, the key is locked, the counting in the third counter 6 stops and the ratio (7) turns into retry (4), Starts (1- | -2) th

the pulse period of the frequency signal F which is processed similarly to the previous one.

Compared with limestone, the proposed pulse frequency multiplying-dividing device has a high speed, since

allows you to perform all the operators for one period of the pulse frequency at the first information input, and allows you to register an increase in the ratio (4) in real time, marked by the pulses coming from the second information input.

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Claims (1)

FREQUENCY-PULSE MULTIPLE-DIVISING DEVICE VO, containing the first and second counters, a delay element, a register, a comparison unit, the first group of information inputs of which are connected respectively to the information outputs of the register, the information inputs of which are connected respectively to the outputs of the first counter, the zeroing input of which through the element the delay is connected to the first information input of the device, the input of the register entry, the counting input of the first counter is connected to the second information input of the device, The third information input of the device is connected to the counting input of the second counter, the output of which is connected to its recording input, characterized in that, in order to increase its accuracy by eliminating dynamic errors, a key and a third counter are inserted into it, the outputs of which are connected respectively to the information inputs the second counter, the recording input of the third counter is connected to the first information input of the device, and the counting input of the third counter is connected to the output of the key, the first input of which is connected to the second information nnym input device, a second input connected to the output of the delay element key, and third key input connected to the output of the comparator, the second group of inputs of which is connected with the respective outputs of the first counter and third counter information inputs, wherein the output of the second counter is a data output device. SU nil 1112364 1 1112364 1