SU1100723A1 - Device for delaying pulses - Google Patents

Abstract

A DEVICE FOR DELAYING PULSES containing the first and second elements AND, the main and additional delay elements, the formers of the front and rear edges, the pulse generator, the first, second and output triggers, the output bus connected to the single output of the output trigger, and the reset bus connected Trigger inputs, characterized in that, in order to extend the functionality by increasing the reproduction accuracy of the input pulse sequence at the output of the device, A pulse shaper, first, second and third circular shift registers and a memory block with a line structure are entered, the device input is connected to the first input of the first element I, the second input of which is connected to the single output of the start trigger, the single input of which is connected to the Start terminal and the zero input is to the Stop terminal, the output of the first element 41 is connected to 1 inputs of the front and rear edges of the drivers, the outputs of which are connected respectively to the single input of the first, zero input of the second trigger The first ring slip register and the single input of the second, zero input of the first trigger, the input of the second ring shift register, the bit outputs of the first and second ring shift registers, respectively, are connected to the second inputs of the first and second groups of the first inputs of which are connected to single outputs of the first and second triggers, respectively, the outputs of the elements And the first group are connected to the inputs of the recording of odd lines of the memory block with a line structure, and the outputs of the elements And the second group ppy - to the inputs of the even recording its rows, the output of said block of each row is connected to the corresponding input of the fourth OR gate, the outputs of odd rows are connected to inputs of the second OR gate, and vyho-§ rows even lines - to an entry; the third t of the OR element, the output of the fourth OR element is connected to the first input of the first OR element, connected by its output to the input of the third ring shift register, and. to the single input of the third trigger, the zero output of which is connected to the second input of the second element AND, the first input of which through an additional delay element is connected to the output of the pulse former and the second input of the first OR element, the input of the primary delayer and with the first inputs of elements And from the third group, the second inputs of which are connected to the bit outputs of the third ring shift register, and the outputs - successively to the writing inputs of each row of the block and a memory with a line structure, the input of the main delay element is connected to the single output of the start trigger, and its other input is connected to the bus. The delay input, output of the second element AND is connected to the first single input of the output trigger, the second single input of which is connected to the output of the third OR element, null:

Description

howling with the output of the second element OR, the reset bus is connected to the installation inputs of all ring shift registers and the memory block from

structure, and the output of the pulse generator is connected to the third inputs of the elements And the first, second and

third groups.

The invention relates to automation, pulsed and computational techniques and can be used in devices for various purposes where it is necessary to obtain a longer delay time of pulse packets, the duration of which and the pauses between them are random.  A device for delaying pulses is known, comprising a generator of so-called pulses, two counters, controlled, connected by an input to a trigger output, a first element AND, another input connected to the output of a clock generator, a main delay conditioner whose input is connected to a device input, a single input the trigger and the fault input of the second counter, the second element I, the inputs of which are connected to the corresponding bitwise outputs of the second counter, n elements I, the rewriting unit and the auxiliary one. the delay driver, the Output of which is connected to the zero input of the trigger and the fault input of the first counter, the output of the main delay driver is connected to the input of the auxiliary delay driver and c. the enable input of the rewriting unit, whose inputs are connected to the corresponding one-bit outputs of the first counter, and the output to the corresponding bit-by inputs of the second counter, the inverse output of the last bit of the first counter is connected to the input of the first element whose output is connected to the inputs of both meters, the inputs of each of The n elements And are connected to the corresponding bitwise outputs of the second counter 1J.  The closest in technical essence to the present invention is a delayed pulse shaper containing counters with memory, a pulse distributor, the input is connected to the device input, and the output is connected to the front edge input of the front pulse generator and the rear edge pulse former.  The output of the front of the pulse front pulse generator is connected to the first input of the first element I, and the output of the back edge pulse former front generator is connected to the first input of the second element I, the second input of which is connected to the single output of the first trigger, and the output to the setup input of this trigger.  A single input of the first trigger is connected to the output of the first element I, the second output of which is connected to the zero output of the second trigger.  On the unit input of the second trigger is connected the unit output of the first trigger and the first input of the third element And, the second input of which. connected to the output of the pulse generator, and the output is connected to the counting inputs of the first counter, the forward output of which is connected to the setup input of the output trigger, the single output of which is connected to the output bus, and the inverse to the first input of the fourth element And, the second input through the delay element connected to the output of the first element And, and the output to the write-off input of the first counter.  The front-edge output of the pulse generator is connected to the first inputs of the sixth and seventh elements AND The output of the sixth element I is connected to the single input of the third trigger.  The second input of the seventh element And is connected to the single input of the third trigger, and the output to the zero input of the latter.  A single output of the trigger trigger is connected to the single input of the fourth trigger, the jule output of which is connected to the second input of the sixth element And and to the second input of the eighth element I.  The first input of the eighth element I is connected to the output of the pulse generator, and the output - to the recording inputs of the second counter, whose input is written off via the second delay element to the output of the fifth And element, the first input of which is connected to the input of the pulse generator, the second input - to the output of the main a delay driver connected by its input to a pulse distributor.  The output of the main delay driver is connected to a single input of the output trigger.  The output of the second counter is connected to the write-off input of the third counter, the recording input of which is connected to the pulse distributor, and the output to the census outputs of the first and second counters, and to the in-one single input of the output trigger. 2T.  The disadvantage of this pulse former is that it is designed to delay the measured sequence, t. e.  such a sequence in which pulses of the same length are contained, as well as pauses between pulses are the same.  If a pulse train of equal length and unequal intervals between them is present at the device input, it cannot be accurately reproduced at the output of the imaging unit.  The purpose of the invention is to expand the functionality by increasing the accuracy of reproduction of the input pulse sequence. owls at the output of the device.  This goal is achieved by the fact that the device for delaying pulses, containing the first and second elements AND, the main and additional delay elements, the formers of the front and rear edges, the pulse generator, the first, second and output triggers, the output bus connected to the unit the output of the trigger output, and the reset bus connected to the setup inputs of the triggers, introduced a pulse shaper, - the first, second and third annular shift registers and a dashboard with a line structure, while the input is It is connected to the first input of the first element And, the second input is connected to the single output of the start trigger, the single input of which is connected to the Start terminal, and the zero input to the Stop terminal, the output of the first And element is connected to the inputs of the front and rear edges of the driver, the outputs of which connected, respectively, to the single input of the first, zero input of the second trigger, the input of the first ring shift register and to the single input of the second, but to the left input of the first trigger, input of the second ring p The shift register, the bit outputs of the first and second ring-shift registers are connected respectively to the second inputs of the AND elements of the first and second groups, the first inputs of which are connected to the single outputs of the first and second triggers respectively, the outputs of the AND elements of the first group are connected to the recording inputs the odd lines of the memory block with the general structure, and the outputs of the elements of the second group - to the inputs of the recording of its even lines, the output of each row of the specified block is connected to the corresponding input of the fourth element or, there are no outputs emnyh lines are connected to the inputs of the second element OR, and the outputs of even lines are connected to the inputs of the third element of the IPD, the output of the fourth element OR is connected to the lane. the first input of the first; tement OR OR, its output with the input of the third ring shift register, and to the single input of the third trigger, the zero output of which is connected to the second input of the second element AND, the first input, which through an additional delay element is connected to the output of the pulse shaper and the second input of the first element OR, the input of the pulse formers is connected to the output of the main delay element and with the first inputs of the elements AND of the third group, the second inputs of which are connected to the discharge outputs tego circular shift register, and outputs - to successively debited. the inputs of each row of the memory cell with the line structure, the input of the main delay element is connected to the single output of the start trigger and its other input to the bus. The input of the delay, the output of the second element I is connected to the first single input of the output trigger, the second single input of which is connected to the output of the third element OR, the zero input - with the output of the second element OR, the reset bus is connected to the installation inputs all. x ring shift registers and a memory block with a line structure, and the output of the pulse generator is connected to the third inputs of the AND elements of the first, second and third groups.  The device is intended to delay the sequence of pulses, the frequency of which and the length of the pulses are random.  The device represents a dynamic discrete pulse delay of a random sequence.  The drawing shows a diagram of the device.  The device for delaying pulses contains the first element. To 1, to the first input of which the Input terminal is connected, and to the second input a single output of the start trigger / 2.  The trigger input is connected to the unit input of trigger 2, and the Stop terminal is connected to the installation input.  The output element And 1 is connected to the pulse shaper of the leading edge 3 and the pulse shaper of the falling edge 4.  The output of the front-edge pulse former 3 is connected to the single input of the first trigger 5, the first setup input of the second trigger 6 and the input of the first annular shift register 7, and the output of the rear-edge pulse former 4 is connected to the first installation input of the first trigger 5, single input of the second trigger b and the input of the second ring register shift 8.  The unit output of the first trigger 5 is connected to the first inputs of the first group of elements AND 9-1 to 9-f to the second inputs of which the outputs of the bits of the first ring shift register 7 are connected.  A single output of the second trigger 6 is connected to the first inputs of the second group of elements I 10-1 -, to the second inputs of which the outputs of the bits of the second ring shift register are connected. The outputs of the generator of pulses 11 are connected to the third inputs of the elements of the first and second groups And elements are connected respectively to the inputs of writing odd and even lines of the memory block with line structure 12.  The input of the main delay element 13 is connected to the output of the trigger trigger 2j and the output is connected to the input of the pulse body 14, and to the first inputs of the third group of elements 15-1 15-2h.  The output of the pulse shaper 14 is connected to the second input of the first element OR 16, the output of which is connected to the input of the third ring shift register 17, the bit HY-H. ODES of which are connected to the second inputs of the third group of elements And 15-1 - 15-2, h, to the third inputs of which the output of the pulse generator 11 is connected, a. their outputs are connected to the write-off inputs of memory 12.  The output of the pulse shaper 14 through the additional delay element 18 is connected to the first input of the second element And 19, the second.  the input of which is connected to the zero output of the third trigger 20.  Element And 19 is connected to the output with the first unit input of the output trigger 21 whose unit output is connected to the Output terminal.  The outputs of the odd lines of the memory block 12 are connected to the inputs of the second element OR 22, the output of which is connected to the first installation input of the output trigger 21.  The outputs of the even rows of the memory block 12 are connected to the inputs of the third element OR 23, the output of which is connected to the second single input of the output trigger 21.  In addition, all the outputs of the memory unit 12 are connected to the inputs of the fourth element OR 24, the output of which is connected to the first input of the first element OR 1 b and to the single input of the trigger 20 The reset bus 25 is connected to the installation inputs of the triggers 2,5,6, 20.  and 21, ring shift registers 7, 8 and 17, and memory block 12.  The storage unit 12 is a set of counters or registers 12-1 to 12-2P, operating only in a sequential code, first in writing, then in reading the number of clock pulses.  Each counter or register has separate write and read control inputs and separate outputs for each of them.  Counters or registers are used as memory elements and as delay elements at the same time.  The device works as follows.  The pulse sequence is fed to the first input element And 1.  If a start signal is applied to a single input of the start trigger 2, then there is a single potential at its single output, which is connected to the second input of the first element I 1.  At the output of the element And 1, a sequence of pulses appears, which is fed to the pulse formers of the front 3 and rear 4 fronts.  When a pulse arrives at the shaper 3, a short pulse appears at its output, which arrives at the single input of the first trigger 5 and translates it into a single state.  In addition / the same pulse arrives at the zero input of the second trigger b and to the input of the first shift register 7.  In the initial state at the bit outputs of the shift register 7, there is no potential.  When the first pulse arrives at the input of the shift register 7, the pulse generator 3 at its output at the first discharge appears a high potential, which is applied to the second output of the first element And 9-1 of the first group of elements 9 9 - 9-fi the first inputs of which have a high potential with one output of the first trigger 5.  The pulses from the generator 11 are now fed through the element AND 9-1 to the input of the recording of the first line of the memory block 12-1.  The storage unit 12 has an inline structure.  Each row 12-1 through 12-2i has a write input, a read input and one output.  This device has a pulse output.  In the case of using memory elements with a potential output at the output of each line of memory 12, it is necessary to supply a shaper of short pulses.  Writing to strings is done sequentially.  The lines with odd numbers (in this case, the count goes from top to bottom) record information in the form of the number of pulses about the pulse length of the pulse sequence, and the lines with even numbers write the length of the pause (the interval between pulses).  The transfer of a record from a string to another is carried out by means of shift registers 7 and 8, and reading is performed using shift register 17.  The pulse length is expressed by the number of Pulses of the generator 11, which passes over the time when the trigger 5 is in the unit state.  At the end of the pulse, the pulse front pulse shaper 4 generates a short pulse that converts the first trigger 5 to zero out, high potential is removed from the first inputs of the first group of elements 9-1 to 9-1L, and the second trigger 6 to one state.  The pulses from the generator 11 are not received in this case in the odd lines of the memory, in particular in the first one.  When overturning -trigger 6 high potential is applied to the first inputs of the second group of elements And 10-1 - 10th.  On the second. the input of the first element And 10-1 is given a high potential from the first discharge of the second shift register 8, since the pulse from the imaging device 4 arrived at the input of the latter.  The pulses from the generator 11 through the third input of the first element And 10-1 are fed to the recording input of the second line 12-2 of the memory block 12.  When the recording of the pause is completed, the pulse length is recorded in the next line.  After the arrival of the next pulse, the shaper 3 selects from the front one. the front is a short pulse which overturns the trigger 5 and translates the register 7 into the next bit.  The recording of pulses, corresponding to the length of the pulses and pauses of the input sequence, was carried out until the last line was used.  With greater delays, different situations may arise.  For example, after writing to the last line, the recording of the meter parameter of the input pulse sequence is stopped.  This information is then read.  Another situation concludes with that the previously recorded information on the input sequence is erased until it is. : wits the signal from the main delay element 13.  Further information is calculated in the order in which it was recorded.  The proposed device addresses the case for delay time V.  .  - length of 1111tulse; - pause length; - the length of the input to the last item,.  which can be written to memory block 12 and which essentially characterizes the required amount of memory selected from the static characteristics of the process under study.  The write-off begins after the appearance of the signal from the output of the main delay element 13.  The selection of the required delay can be done in various ways: either manually or automatically (in the diagram this is designated as the input of the delay).  The delay element 13 is turned on by a signal from the output of the trigger trigger 2, which in the form of a potential is fed to the input of the delay element 13.  In case the triggering element 13 is triggered by a pulse, a shaper of short pulses must be provided at the output of the trigger trigger 2.  The output signal from the main delay element 13 is fed to the first inputs of the And 15-1 elements - 15-2p of the third group and to the pulse shaper 14, which produces a short pulse to start the additional delay element 18 and transition the third shift register 17 to the first bit through the first the input of the first element OR 16.  The register 17 generates from the first discharge a high potential to the second input of the first element 15-1 of the third group, ensuring the passage of pulses from the generator 11 to the reading input of the first row 12-1 of the memory block 12.  The delay element 18 is necessary so that the pulse to start the output trigger 21 does not pass before the status of the first row 12-1 of the memory block 12 is checked.  The delay time of the element 18 is chosen so that the pulse from the output of the first line of the memory block 12, if it contains zero, overturned the trigger 20 earlier than the i-pulse passes to the first input of the second ele. . .  ment and 19 with delay element 18.   Next, a read is made from another STRING, in which s. The length of the pause is written.  At the end of reading the number from the second line, a pulse appears at its output, which through the fourth element OR 24 to the first element OR 16 transfers the third ring shift register 17 to the third bit and sets the trigger 20 to the one state.  The same pulse through the third element OR 23 translates the output trigger 21 into a single state, and a high potential appears on the output terminal.  Next, the number is written off from the third line of the memory block 12, at the end. a pulse appears at its output, which translates the shift register 17 into

the fourth bit, and the trigger 21 through the second element OR 22 sets to the zero state and a low potential appears on the output terminal. In the future, the operation of the device is repeated. After reading the information, the line is reset. The writing and reading process takes place simultaneously. When a pause is written on the last line, the circular shift registers 7 and 17 are transferred to the first bit. The writing and reading process continues until the signal is applied to the Stop terminal.

The accuracy of the reproduction of the pulses and pauses is determined by the frequency of the sh-pulse generator 11. However, an increase in the frequency leads to an increase in the length of the line of the memory block.

The proposed device allows obtaining a wide range of delayed sequences of pulses with random lengths of pauses, saves information about each pulse and each pause, and, thus, has more extensive functionality than the base prototype object.

Claims (1)

A device for delaying pulses, containing the first and second elements AND, the main and additional delay elements, pulse shapers, leading and trailing edges, a pulse generator, first, second and output triggers, an output bus connected to a single output of the output trigger, and a reset bus, connected to the installation inputs of the triggers, characterized in that, in order to expand the functionality by increasing the accuracy of reproducing the input pulse sequence at the output of the device, given the pulse shaper, the first, second and third ring shift registers and a memory block with a lowercase structure, while the input of the device is connected to the first input of the first element And, the second input of which is connected to a single output of the trigger, the single input of which is connected to the Start terminal, and zero input - to the Stop terminal, the output of the first element AND is connected to the inputs of the shapers of the leading and trailing edges, outputs. which are connected respectively to the single input of the first, zero input of the second triggers, the input of the first ring shift register and to the single, input of the second, 'zero input of the first triggers, the input of the second ring shift register, the bit outputs of the first and second ring shift registers are connected respectively to the second the inputs of the elements And the first and second groups whose first inputs are connected to the unit outputs of the first and second triggers, respectively, the outputs of the elements And the first group are connected to the inputs si of odd lines of a memory block with a line structure, and the outputs of AND elements of the second group are connected to the entries of its even lines, the output of each line of the indicated block is connected to the corresponding input of the fourth OR element, the outputs of the odd lines are connected to the inputs of the second OR element, and the output is § of even lines'- to the inputs of the third OR element, the output of the fourth OR element is connected to the first input of the first OR element connected by its output to the input of the third ring shift register, and. to one; to the third trigger input, the zero output of which is connected to the second input of the second AND element, the first input of which through an additional delay element is connected to the output of the pulse shaper and the second input of the first OR element, the input of the pulse shaper is connected to the output of the main delay element and to the first inputs of the AND elements * · The third group, the second inputs of which are connected to the bit outputs of the third ring shift register, and the outputs are sequentially to the write-off inputs of each line of the memory block structure, the input of the main delay element is connected to a single output of the trigger, and its other input is connected to the bus Delay input, output of the second element AND is connected to the first single input of the output trigger, the second single input of which is connected to the output of the third element OR, is null SU U100723 input is with the output of the second OR element, the reset bus is connected to the installation inputs of all ring shift registers and a memory block with a line structure, and the output of the pulse generator is connected to the third inputs of the And elements of the first, second and third groups.