SU1492473A1 - Counter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital information processing devices. The purpose of the invention is to increase the reliability of the device. The device contains input bus 1, installation bus 2, memory array 3, installation block 4, address counter 5. The introduction of the buffer register 6, the adder 7, the pulse generator 8 and the decoder 9 allows an increase in the capacity of the counting device without a proportional increase in the number of elements used. 3 il.

Description

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The invention of otyosicht to the pulse technique and can 6i, iTii ispo. i.chonan p digital processing equipment information.

The purpose of the invention is to understand the reliability of devices; by simplifying it.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - pulse p pulse generator; in fig. 3 - unit installation.

The device (Fig. 1) contains an input igina 1, a spike 2 of the installation, a matrix 3 gtam TiU installation block A, a counter 5 of the address, a buffer register 6, an adder 7, a driver of 8 pulses and a 1H1 generator of zero ad-jieca, the output of which is connected to the installation the entrance of the fop importer. and the sync input of the installation unit, the first output of the latter is connected to the installation input of the address counter, and the second output to the installation input of the buffer register, to the transfer input of the adder and to the first control input of the pulse former, the second control input of which is connected to the transfer output of the adder, } 1a 2 of the installation is connected to the information input of the installation unit, input bus 1 is connected to the synchronous inputs of the counter 5 of the address, 1H1frator 9 of the zero address and the pulse former, the first output of the last connection en to the synchronous input of the buffer register, and the second output to the input of the recording of the memory matrix, the information outputs of the 5 address- I counter are connected to the information

the inputs of the decoder are 9 zero addresses and with the address} the 1st inputs of the memory matrix. The information inputs and outputs of the buffer register are connected respectively to the information outputs of the memory matrix and to the first inductance inputs of the adder, the second information inputs of which are connected to the zero bus, and the information inputs to the memory matrixes.

Pulse generator 8 (Fig. 2 contains the first 10, second 11 and third 12 AND-NES elements, inverter 13 and trigger 1A, the clock input of which is connected to the output of the first AND-NEA element and is the second output of the pulse shaper, asynchronous trigger setting input 14 in 1 in

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It is set to 1 () 1K) input of the pulse former, the inverse trigger output is connected to the first (, um input of the third AND-NE 12 element, the second input of which is the first control input of the pulse former, and the output is connected with the first inputs of the first 10 and second 11 elements I-PE, the second input of the first element AND-NOT is connected to the output of the inverter 13, the input of which is connected to the synchronizer input of the pulse driver and to the second input of the second element AND-NOT, the output of which is the first output of the driver pulses.

Installation unit 4 (FIG. 3) contains first 15 and second 16 triggers and AND unit 17, the output of which is the first input of the installation unit and connected to the information input of the second trigger, the output of which is the second output of the installation unit, and the clock input is connected to the clock input of the first trigger is the synchronization input of the installation unit, the first input of the AND element is connected to the output of the first trigger, and the second input is connected to the information input of the first trigger and is the information input of the installation unit.

After switching on the supply voltage, the state of the triggers 14 and 16, the counter 5, the address and the memory matrix 3 are undefined.

The condition of the trigger 15 can be neglected, since the logical bus O is present on the bus 2 of the plant. Therefore, a zero level is created on the first output of the unit 4 of the plant, which does not interfere with the operation of the 5 address counter.

When a pulse sequence is applied to the input bus 1 after a series, the address counter 5 becomes in the position corresponding to the zero state.

The decoder 9 generates a pulse of zero address, which is fed to the clock input of the trigger 14 of the pulse shaper and the clock input of the trigger 15 and 16 of the installation unit.

Assume that the inverse output of the trigger 15 is zero potential. Then, taking into account that on bus 2, a set-up}, connected to informational D-input of trigger 16, there is a zero potential (there is no setting signal), the impulse from the decoder

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9 transfers the trig er 15, but the state at the first output of the installation unit does not change and is still equal to zero potential. If the second output of the installation unit A (inverse output of the trigger 16) has zero potential, then at the moment of arrival of the pulse to the clock input of the trigger 16 there is a zero potential at the information output, the trigger 16 is reset and a high potential is set at the second output of the installation unit.

In addition, the pulse at the input-ioNry input posts 8 pulses on the driver, i.e. on the S-input trigger 1A. Assume that the trigger 14 is set by an impulse on the S input, i.e. on the inverse output, a zero shade appears.

The high level from the trigger 16 (inverse output) is fed to the input element AND IS NOT 12, and the second input of this element receives a low level. At the output of element 12, there is a high potential, which is maintained in the open state by elements 10 and 11. At their outputs, there are forward and reverse input pulse sequences.

During the passage of a zero address pulse, a high output is present at the second output of the pulse generator.

the cue level, which corresponds to the reading mode from the matrix 3, is memory:;; and at the first output of the imaging unit S pulses - a low ypoFteHb, which corresponds to the write mode to the buffer,

now register 6.

 However, taking into account that at the second output of block 4 of installation logical 1 at the transfer input of adder 7 and the resolution of the buffer register 6, the operation of the device is not considered, since the result in this case is not predictable. The main result of the considered variant is the installation of the triggers 14, 15, 16,

On the bus 2 signal installation, the duration of which must be longer than the duration of the counter 5.

Since the inverse output of the trigger 15 is high and the installation signal is characterized by a high level, then at the output of the element I 17 cos

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It also provides: a high level, which resets the counter 5, which corresponds to its degeneration to the zero state. As a result, a zero address impulse is generated, which flips the trigger 16, the trigger 15 (at the inverse output is the zero level) and the trigger 14 (at the inverse output is the zero level).

When the pulse of the zero address is completed, the state of the counter 5 of the address does not change, the buffer register 6 is in the zero state, the memory matrix 3 goes into recording mode, in which the zero cell also records zero.

On the rising front of the first pulse (input sequence from bus 1), the address counter 5 changes its state and sets the addresses of the first cell.

In this case, the state of the second output of the installation unit 4 also does not change, the state of the buffer register 6 is zeroed. At the end of the pulse (in pause), the memory matrix 3 goes into recording mode and the first cell has O.

The memory reset matrix 3 cycle lasts for a time determined by the capacity of the address counter 5 and the period; 1 ° "following the input pulse sequence.

As soon as the address counter 5 returns to the zero state, at the output of the decoder 9 a zero address pulse appears, which sets a high level on the inverse codes of the trigger 15 and 16, since the information input of the trigger 15 has a zero level.

A high level at the second upstream of the installation unit removes the potential of the zeroing buffer register 6; in addition, it corresponds to the analogical 1 current acting at the transfer input of the adder.

Upon expiration of the zero address pulse, the state of the counter 5 of the address does not change, the buffer register 6 is in the read mode. From buffer register 6, O is read. Considering 1 at the transfer input, from the output of the adder 7 1 is written into the first cell of the memory matrix 3, since its potential input acts at a low potential.

,, Consider the state in which the Rcex bits of the zero cell of the memory 3 matrix are written 1. At the moment of the zero address, the zero cell is read and written into the buffer register.

At the end of the zero-address pulse, the buffer register goes into read mode, and the matrix of 1 m tee goes into write mode, while the count of 5 counter of the address has not changed yet and corresponds to the address of the i-th zero cell.

All units from buffer register 6 are fed to adder 7, at the transfer input of which is also present 1. As a result, 1 appears at the transfer output, and O is received to write to the zero cell.

The first pulse sets the address counter 5 to the state corresponding to the first cell, and triggers the pulse generator 14 to a state in which a low level appears at its inverse output.

During the next pulse, the first matrix of memory 3 is in read mode and sends O, and the buffer register 6 is in write mode and sends these O.

Upon termination of this pulse, the buffer reg ister goes into the read mode, and the first cell goes into the write mode. Since in the buffer register 6 - O, there is 1 at the input of the transfer of adder 7, then at the output of adder 7 there is 1 in M1th order, which is recorded in the first cell.

Counter 5 of the address fulfills the cycle, the impulse of the zero address is re-organized, and the cycle of recording information in the zero cell until it is filled, repeats.

Claims (1)

Invention Formula A counting device containing an input bus, 1S1 on the installation, matrices, address counter, an installation block, characterized in that, in order to increase reliability by simplifying it, a buffer register, an adder, a pulse driver and a zero address decoder, output which is connected to the installation input of the pulse former and with the synchronous input of the unit five 0 five 0 five 0 five 0 5 installation, the first output of which is shown to the installation input of the address counter, and the second output to the installation | The new input of the buffer register, the transfer input of the adder and the first control input of the impulse generator, the second control input of which is connected to the transfer output of the adder, the installation width is connected to the information input of the installation unit, the input bus is connected to the synchronous inputs of the address counter, the zero address decoder and the former pulses, the first output of which is connected to the synchronous input of the buffer register, and the second output - to the input of the recording of the memory matrix, the information outputs of the address counter are connected to the inform information inputs and outputs of the buffer register are connected respectively to the information outputs of the memory matrix and to the first information inputs of the adder, the second information inputs of which are connected to the zero bus, and the information outputs to the zero bus the form and the first inputs of the memory array, the pulse shaper comprising the first, second and third elements of NAND, inverter and trigger, the clock input of which is connected to the output of the first element IS-NOT is the second output of the pulse generator, the input of the asynchronous trigger setting to 1 is the installation input of the pulse generator, the inverse output of the trigger is connected to the first input of the third AND-NOT element, the second input of which is the first control input of the pulse generator, and the output is connected to the first inputs of the first and second elements AND-NOT, the second input of the first element AND-NOT connected to the output of the inverter, the input of which is connected to the synchronous input of the pulse former and to the second input of the second element AND-H whose output is the first output of the pulse generator, and the installation unit contains in its composition the first and second triggers and the AND element, the output of which is the first input of the installation unit and connected to the information input of the second trigger, the output of which is the second output of the installation unit and clock the input is connected to the clock input of the first trigger and is the synchronization circuit of the installation unit, the first input of the AND element is connected to the output of the first trigger, and the second input is connected to the information input of the first trigger and is the information input of the installation unit. I about 13 and 15 Editor N. Gunko Fig.Z Compiled by P. Smirnov Tehred A. Kravchuk i 12 g / " Ts3i2.1 And ten 17 sixteen eight 15 Proofreader M. Vasiliev