JP2845289B2 - High-speed synthesis method of image data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for synthesizing image data at high speed, and more particularly to a method for alternately arranging data in first and second image memories in a third memory at high speed.

[0002]

2. Description of the Related Art In an image sensor tester (CCD test / inspection apparatus) or the like, every frame (one screen)
The image data output from the CCD (Charge Coupled Device) of the ch (channel) output type is once written to the first and second image memories, respectively, and then the data of the first and second image memories are read to obtain the third image. Writing the data in the memory in an alternately arranged state, that is, synthesizing the image data on the third image memory is performed. In FIG. 5, it is assumed that the data to be combined {A _i } and {B _i } for one frame are written in the memories 1 and 2 as shown in FIGS. 6A and 6B, respectively. As shown in FIG. 6D, the data is written in the memory 3 in an alternately arranged state. Conventionally, first, data {A _i } in memory 1 is:
A ₀ A ₁ A ₂ ... Are read out in the order of addresses input from the address pointer (a type of counter) 6a, and written in the odd-numbered columns of the memory 3 sequentially from the first row (FIG. 6).
C). The write address in the memory 3 is provided by an address generator 7 . Next, the data {B _i }
Are read as B ₀ B ₁ B ₂ ... In the order of addresses input from the address pointer 6b, and written in the even-numbered columns of the memory 3 sequentially from the first row (FIG. 6D). As described above, new image data in a state where the data A _i and _Bi are alternately arranged is created in the memory 3.

[0003]

In the conventional image data synthesizing method, when writing data in the memories 1 and 2 to the memory 3, the addresses generated by the address generator are discrete addresses in every other column. . When data is written by continuous addresses, the data can be written at a high speed by a known interleave method. That is, one data can be written every one clock cycle (one machine cycle) T. However, in the case of discrete addresses, the interleave method cannot be used, so that the time required for writing one data is significantly slowed down to, for example, (8 to 16) T. For this reason, there is a disadvantage that high-speed synthesis of image data cannot be performed. SUMMARY OF THE INVENTION An object of the present invention is to solve such a conventional disadvantage and to provide a high-speed synthesizing method of image data.

[0004]

SUMMARY OF THE INVENTION The present invention relates to a high-speed synthesizing method of image data to be written in a third memory in a state where data recorded in a first and a second image memory are alternately arranged. In the present invention, the data in the first and second memories are sequentially read out, and the fourth and fifth data are sequentially read at every one clock cycle (one machine cycle) T.
Primary source to write into the memory, in the fourth, the data respectively-written in the fifth memory is input to the multiplexer out read <br/> the order in which they were written by the 2T cycle, the multiplexer, the second Fourth, data input from the fifth memory is alternately selected for each T time, input to the third memory, and sequentially written to consecutive addresses.

[0005]

An embodiment of the present invention will be described with reference to the drawings. In FIG. 1, parts corresponding to those in FIG. 5 are denoted by the same reference numerals. FIG. 2E is based on the image data {A _i }, {B _i } (FIGS. 2A and B) of the memories 1 and 2 in FIG.
As shown in (1), data in which data A _i and _Bi are alternately arranged is written into the memory 3 at high speed. According to the present invention, first, data {A _i }, {B _i } of memories 1 and 2 are simultaneously and successively read at every clock cycle T, and are sequentially stored in memories 4 and 5 as shown in FIGS. written primary original manner at the same speed as the. Next, memory 4
Of data {A _i } are sequentially read at a time interval of 2T, and data {B _i } of memory 5 is sequentially read at a time interval of 2T with a delay of T time. The output data of these memories 4 and 5 are alternately selected by the multiplexer 8 at every T time and are continuously written in the memory 3. A write enable signal W _E (FIG. 3B) is supplied from a data transfer timer 11 from the memories 1 and 2 to the memories 4 and 5 to the preset signal generator 12, and a preset signal P _W (FIG. 3C) is generated. , 14, the address input terminals A of the address pointers 15, 16
Respectively. As a result, both pointers are cleared, and the addresses PA = PB = 0, 1,
Are generated every clock cycle T, and the memories 4, 5 are generated.
, Respectively. Image data {A _i } and {B _i } are output from the memories 1 and 2 at the same timing as the data of the addresses PA and PB, in the order of addresses, for T time, and supplied to the memories 4 and 5, respectively. The memories 4 and 5 are called, for example, FIFO memories (output in the order of input data). In the memories 1 and 2, a continuous address (x direction,
according y direction of the two-dimensional specific address), image data {A _i}, the {B _i} is output in order from the first row at every T time.

[0006] The preset signal P _W is also supplied to the write pulse generator 18, and when the P _W falls, the clock CLK becomes higher.
The write signal _SW (FIG. 3G), which is delayed by approximately T / 4 time, is generated and given to the write enable terminals WE of the memories 4 and 5. In the memories 4 and 5, each time the write pulse _SW is turned on, the input data {A _i }, {B _i } is specified in numerical order by the input address PA = PB = {i} = 0, 1, 2,. the memory cells, in synchronization with a falling edge of the clock, is written primary source to write sequentially (Fig. 3H,
I; FIGS. 2C, D). Thus, the image data in the memories 1 and 2 are transferred to the memories 4 and 5 at the same speed as the clock. A read enable signal R _E (FIG. 4B) is provided from a data transfer timer 11 from the memories 4 and 5 to the memory 3 to a preset signal generator 22 to generate a preset signal P _R (FIG. 4D). It is supplied to the preset terminal P of the pointer 15. Meanwhile, the preset signal P _R is delayed tau ₁ = T time through the delay circuit 23, the preset signal P _R '(FIG. 4
H), and supplied to the preset terminal P of the address pointer 16 through the OR gate 14.

[0007] The preset signal P _R is supplied to the hold signal generator 24, the hold signal H _a, H _b (FIG. 4
E, F) are created and supplied to the hold terminals H of the address pointers 15, 16, respectively. In the address pointer 15, from immediately after the preset by the preset signal P _R, it counts the rising edge of the clock CLK,
The count value {i} = 0, 1, 2,...
To the memory 4. The hold terminal H of the address pointer 15 is given every other hold signal becomes H level H _a clock is, since the count value is held at its time, the output PA of the address pointer 15 for each 2T +1 (FIG. 4G). Similarly, in the address pointer 16, after being cleared by the preset signal P _R ′, the address data P which is incremented by 1 in a period of 2T time.
B = {i} = 0, 1, 2,... Are output (FIG. 4J).

[0008] a write enable signal input in the memory 4, 5 W _E is at the L level, is in the read mode, the address signal PA, the PB is given (in the example of FIG. 4 1.5T) a predetermined time has elapsed Later, in synchronization with the falling edge of the clock, the corresponding data A ₀ A ₁ A ₂ ... And B ₀ B ₁ B
₂ are output (K and L in FIG. 4) and supplied to the data input terminals A and B of the multiplexer 8. Data A _i, the time length of B _i is equal to the time length 2T of course address signal.

On the other hand, hold of the hold signal generator 24
Signal H_aIs τ through the delay circuit 26 _Two= 1.5T delay
Select signal S which becomes H or L every T time_S(FIG. 4
I) is made and applied to the select terminal S of the multiplexer 8.
Has been obtained. In the multiplexer 8, the input signal
｛A_i｝, ｛B_i｝ Is the select signal S_SBy T time
Output signal A₀B₀A₁B₁A_Two
B_Two.. Are supplied to the memory 3.

Address signals a ₀ , a ₁ , a ₂ ... (FIG. 4N) are supplied from the address generator 7 to the memory 3 in accordance with the timing of the data input from the multiplexer 8. The first row, the second row,... Are written at successive addresses at every time (FIG. 2E). In addition,
In the embodiment shown in FIG. 1, the timings of the preset signals P _R and P _R 'applied to the address pointers 15 and 16 are shifted by T time from each other, whereby the timings of the address signals PA and PB applied to the memories 4 and 5 are shifted by T time. , Whereby the output data {A _i },
Although the timing of {B _i } is shifted by T time, the present invention is not limited to this case, and the preset signals P _R and P
_R ′ and the address signals PA and PB are common,
Thereby, the timings of the output data {A _i }, {B _i } are matched, and the data A _i , B _{i in} the first half and the second half of the 2T cycle.
May be alternately selected. Obviously, this makes the hardware more economical.

[0011]

[Effect of the Invention] be-combined data of first memory 1 according to the present invention _{{A i}, {B i} } is (every clock period T), respectively at a high speed in the memory 4, 5 primary sequentially <br /> Written originally. Next, the data {A _i }, {B _i } written in the memories 4 and 5 are sequentially read at a 2T cycle, are alternately selected by the T time by the multiplexer 8, and are sequentially stored at successive addresses of the memory 3 ( (Every T hours). Therefore, according to the present invention, the combined data (data in which the data in the memories 1 and 2 are alternately arranged) is stored in the memory 3
The time T ₀ required to obtain the data T ₁ is the time T _A for transferring the data in the memories 1 and 2 and writing the data in the memories 4 and 5 at every T time, and the time T 2 for reading the data in the memories 4 and 5 at a 2T cycle. ,
It is almost equal to the sum of the times T _B (≒ 2T _A ) for alternately writing to the memory 3, and therefore T ₀ ≒ 3T _A. On the other hand, in the conventional method, the time T ₀ is the sum T _{1 of} the times T ₁ and T ₂ required for discretely writing the data in the memories 1 and 2 to the memory 3.
₀ ≒ T ₁ + T ₂ , for example, T ₀ ≒ 2 × (8 to 16)
It is extremely slow and T _A. Therefore, according to the present invention, it can be seen that the time required for synthesizing the image data can be made much faster than in the past.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a memory circuit to which an embodiment of the present invention is applied.

FIG. 2 is a view showing an arrangement state of data in memories 1 to 5 in FIG. 1;

FIG. 3 is a timing chart in the case of transferring data in memories 1 and 2 to memories 4 and 5 in FIG.

FIG. 4 is a timing chart in the case of transferring data of memories 4 and 5 to a memory 3 in FIG.

FIG. 5 is a block diagram of a memory circuit to which a conventional image data synthesizing method is applied.

FIG. 6 is a diagram showing a recording state of data in memories 1 to 3 in FIG. 5 ;

Claims (1)

(57) [Claims] 1. A high-speed synthesizing method of image data to be written to a third memory in a state where data respectively recorded in a first and a second image memory are alternately arranged. read sequentially Te, 1 clock cycle (one machine cycle), respectively fourth sequentially for each T, fifth memory to the primary source to write, the fourth, respectively-written data in the fifth memory 2
The data is read out in the order written in the T cycle and input to the multiplexer. In the multiplexer, the data input from the fourth and fifth memories are alternately selected for each T time and input to the third memory. A high-speed image data synthesizing method characterized by sequentially writing data at specified addresses.