JP2976991B2 - High-speed image data extraction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed image data extracting apparatus for an image sensor tester (CCD test and inspection apparatus).

[0002]

2. Description of the Related Art In a conventional image sensor tester (FIG. 5), as shown in FIG. 6A, image data D _1,1 D _1,2 D _1,3
.. _Are extracted from the memory in which... Are stored at specific addresses in parentheses (D _1,1 ) (D _1,3 ) (D _1,5 ).
As shown in B, writing is performed at consecutive addresses in the memory 2. The reason is that if data is written to consecutive addresses in the memory as described above, the data can be transferred at a high speed using a well-known interleave method when transferring the data. In that case,
Data D _1,1 D to be extracted from address generator 5
_{1, 3} D _{1, 5} ... are generated addresses A _{1, 1} A _{1, 3} A _{1, 5} ... is sequential, are supplied to the address input terminal A of the memory 1, the data from the memory 1 accordingly (D _{1, 1} ) (D _1,3 )... _Are sequentially output. On the other hand, the address pointer 6 Y direction address Y ₁ showing from the first row of the memory cell and the address in the X direction of the order X ₁ X ₂ X _3, likewise second row address Y
₂ and _{X 1 X 2 X 3, Y} 3 and X ₁ X ₂ X ₃ is generated, de
The signal is supplied to the address input terminal A of the memory 2 via the multiplexer 7 . In the memory 2, as shown in FIG. 6B, the input data (D
_1,1 ) ( _D1,3 )... Are sequentially written.

[0003]

In the prior art, when data at a specific address is extracted from the memory 1 and transferred to the memory 2, so-called random access is performed on the memory 1, so that an interleave method is used. Therefore, there is a disadvantage that the time required for data transfer becomes extremely long (for example, about eight times that in the case of using the interleave method). SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional drawbacks and to shorten the data transfer time from the memory 1 to the memory 2.

[0004]

A high-speed image data extracting apparatus according to the present invention comprises a first memory from which data written to an address specified by an address generator is read, and a storage capacity of the first memory. Have the same storage capacity, store logic "1" at the same address as the specific address of the first memory, and store logic "0" at the other addresses;
When the same address as the address of the first memory is simultaneously designated from the address generator and the written data is read out, and in a write mode,
Means for generating a write signal in accordance with a logic "1" of the data read from the third memory, and counting a logic "1" in the data read from the third memory in the write mode, At the time, the data read from the first memory is stored by the write signal at the address designated by the address pointer in the address pointer for counting the clock and in the write mode in the write mode, and is stored in the read mode. Data from the address specified by the address pointer to a fourth memory read by the clock; and data stored in the fourth memory read by the clock to the address specified by the address generator. The second memory stored by the clock and the demultiplexer in the write mode. Through the support to supply an address to sequentially sequentially in the first memory, when the read mode, anda address generator provides address sequentially to the second memory sequentially via the demultiplexer.

[0005]

FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. According to the present invention, memories 3 and 4 are added in addition to the memory 1 in which image data is written and the memory 2 in which data at a specific address of the memory 1 is to be extracted and written to a cell having continuous addresses. The data in the memories 1 and 2 are the same as those in FIGS. 6A and 6B described in the conventional example. As shown in FIG. 2A, the memory 3 stores data of a specific address to be transferred to the memory 4 .
Logic "1" is written in the same address as the address of each cell, and logic "0" is written in the other addresses.
Is for sequentially writing data (D _1,1 ) (D _1,3 )... Transferred from the memory 1 as shown in FIG. 2B.

In the present invention, first, data in the memory 1 is sequentially read out at high speed by a known interleave method, and only data at a specific address to be extracted is sequentially written into the memory 4, and then data in the memory 4 is read out. Are sequentially read at high speed sequentially by the interleave method, and are sequentially written into the cells of the first row, the second row,.

Data transfer from the memory 1 to the memory 4 In synchronization with the clock CK (FIG. 3A) from the address generator 5, the address of each cell of the memories 1 and 3 is A _1,1 A _1,2 A _{1, 3} A _1,4 A _1,5 A _1,6 A _2,1 A _2,2 ... _Are sequentially output and the terminal a of the demultiplexer 7
, And is supplied to each address input terminal A of the memories 1 and 3 (FIG. 3B). As a result, after a predetermined time (2 × T in the example of FIG. 3; T is a clock cycle) after the address signal A _1,1 A _1,2 .
Data (D _1,1 ) D _1,2 (D _1,3 )... Of each address are output at high speed by a known interleave method (FIG. 3).
C).

Similarly, a signal S ₀ (the signal shown in FIG. 3D, also referred to as an extraction command signal) which becomes H (high level) during the output time of the data at a specific address to be extracted from the memory 3 is interleaved from the memory 3. The data is read out at a high speed by the method, applied to the AND gate 8, and the clock CK and AND are taken. The output of the AND gate 8 is delayed by τ ₁ ≒ T / 4 time through the delay circuit 9 (as described later, the same as the signal S ₂ in FIG. 3G) and applied to one input terminal of the AND gate 10. On the other hand, when the memory 4 is in the write mode, the read signal S ₁ (which becomes H when the memory 4 is in the read mode) from the read signal generator 11 (FIG. 3)
I) is generated, inverted to the H level by the inverter 12, and given to the other input terminal of the gate 10, and the AND gate 10 is open. AND Gate 1
An output S _{2 of} 0 (a signal shown in FIG. 3G and called a write enable signal) is given to a write enable terminal WE of the memory 4.

The output of the memory 3 (FIG. 3D) is
Τ ₂ ≒ T / 2 time through the OR gate 16
Is applied to one of the input terminals. The output S _{3 of the} OR gate 16 (FIG. 3E) is given to the count-up signal input terminal CU of the address pointer 6. The address pointer 6 is a kind of counter, and the count-up signal S ₃ is H
, The count value N is incremented by +1 every time the clock CK rises.
The input addresses N, N + 1, N + 2, N + 3,... Are input to the address input terminal A (FIG. 3F).

[0010] In the memory 4, the write enable signal S ₂ for the first time becomes H, the input data (D _{1, 1)}
Is written to the memory cell at address N in synchronization with the falling edge of the clock (FIG. 3H). When the write enable signal S ₂ is re Tabi H, the input data (D _{1, 3)} is, in synchronization with a falling edge of the clock, is written into the memory cell (N + 1) address (Fig. 3H). Similarly, the address pointer 6
, The data (D _1,5 ) (D _2,2 ) extracted from the memory 1 are sequentially written in the cells at addresses N + 2, N + 3,. FIG. 2B shows the memory 4 extracted from the memory 1
3 shows the data written in.

Transfer of Data from Memory 4 to Memory 2 In order to switch the memory 4 from the write mode to the read mode, the output S ₁ of the read signal generator 11 is switched from L to H (FIG. 4B). Therefore, the output of the inverter 12 becomes L from H, the AND gate 10 is closed, and the memory 4
Write enable signal S ₂ of becomes L, the read mode. At the same time, the input terminal a of the demultiplexer 7 is switched and connected to the output terminal c.

[0012] count-up signal S ₃ of the address pointer 6, the lead signals S ₁ is at H, always H level, and counts clock CK (FIG. 4A), the output signal N, N + 1, N + 2, N + 3, ... Is input to the address input terminal A of the memory 4 (FIG. 4).
C). After a lapse of a predetermined time (2T in the example of FIG. 4) from the application of the address signal to the memory 4, the corresponding data D _1,1 D _1,3 D _1,5 D _2,2 . Output.

On the other hand, in the address generator 5, the address signal (FIG. 4E) A _1,1 A _1,2 A _1,3 A _2,1 A _2,2 is synchronized with the data output from the memory 4. Are generated and supplied to the address input terminal A of the memory 2 via the demultiplexer 7 . Further, a write enable signal S ₄ (FIG. 4F) obtained by delaying the clock by τ ₃ ≒ T / 4 time through the delay circuit 17 is generated and supplied to the write enable terminal WE of the memory 2. The data D _1,1 first input to the memory 2 is a write enable signal S ₄
Becomes H, the data is written into the cell at the input address _A1,1 in synchronization with the falling edge of the clock (FIG. 4G). Next, the data D _{1, 3,} which is input to the memory 2, a write enable signal S ₄ is H, are similarly written to the cells of the address input address A _{1, 2.} Similarly, data D _1,5 , D _2,2
.. _Are written to addresses A _1,3 A _2,1 . In this way, the specific data extracted from the memory 1 is written into the memory 2 as shown in FIG. 6B.

Although the storage capacity of the memory 3 may be the same as that of the memory 1, it is sufficient that the storage capacity is at least the same as the storage area of the image data in the memory 1.

[0015]

According to the present invention, data read from the memory 1 is successively read one by one in the order of addresses. Therefore, the data is read at an extremely high speed by using the interleave method as compared with the conventional random access. be able to. Among these read data, the extraction command signal S ₀ which becomes high level in synchronization with the output timing of the data to be extracted.
Because There is output from the memory 3, the data to be extracted based on the extracted command signal S ₀ in the memory 4, the memory 1
Can be sequentially written during the data output period T _{A of} .

The data in the memory 4 is stored in a sequencer.
At high speed by the interleave method,
Readout period T_BIn the first row, the second row of the memory 2,
.. Can be written continuously to each cell. Therefore
In the present invention, the data to be extracted from the memory 1 is stored in the memory 2
Time T required for transfer_OIs for reading data from memory 1
Interval T_AAnd data read time T of memory 4 _BSum time with
Is approximately equal to Therefore, according to the present invention, during this transfer,
Interval T_O≒ T_A+ T_BUses traditional random access
It is clear that the speed can be much faster than
is there.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory circuit to which an embodiment of the present invention is applied.

FIG. 2 is a view showing an example of data written in memories 3 and 4 in FIG. 1;

FIG. 3 is a timing chart of main parts when specific data is extracted from a memory 1 and written into a memory 4 in FIG.

FIG. 4 is a timing chart of a main part when data in a memory 4 is transferred to the memory 2 in FIG. 1;

FIG. 5 is a block diagram of a memory circuit to which a conventional data extraction method is applied.

FIG. 6 is a view showing an example of data written in memories 1 and 2 in FIGS. 1 and 5;

Claims (1)

(57) [Claims] A first memory from which data written to an address specified by an address generator is read; a first memory having a storage capacity equal to the storage capacity of the first memory, and the same as a specific address of the first memory; A logic "1" is stored in the address and a logic "0" is stored in the other addresses, and the same address as the address of the first memory is simultaneously designated from the address generator, and the written data is read out. A memory, means for generating a write signal in accordance with a logic "1" of the data read from the third memory in the write mode, and a memory for generating a write signal in the write mode. An address pointer that counts the logic "1" and counts the clock in the read mode, and specifies the address pointer in the write mode. A fourth memory in which data read from the first memory is stored at the address by the write signal, and in a read mode, the stored data is read from the address specified by the address pointer by the clock; The data stored in the fourth memory read out by the clock is stored in the address specified by the address generator, the second memory stored by the clock, and via a demultiplexer in the write mode. The first
An address generator for sequentially supplying addresses to a memory sequentially and supplying addresses sequentially to the second memory via the demultiplexer in a read mode in a read mode.