JPS61142814A - Digital delay device - Google Patents

Abstract

PURPOSE:To obtain a high-speed digital delay device by dividing an address space into halves for the memory cell groups set in a matrix form and secures an access of each space with a prescribed clock pulse. CONSTITUTION:An address space accordant with a delay amount is divided into two memory cell arrays 84 and 94. Each of both arrays 84 and 94 performs a read-modified-write action within an address cycle double as much as a basic clock pulse phiS. Then the phases of address cycles are shifted from each other by a cycle of the pulse phiS between both arrays 84 and 94. The read data of both arrays are delivered alternately in a clock rate of the pulse phiS. Then the input data supplied in said clock rate are stored alternately to both arrays.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital delay device, and more particularly to a digital delay device used, for example, in video signal processing of a digital television receiver.

[Prior Art J Conventionally, as a large-capacity digital delay means, sequential reading is performed to memory cells arranged in a matrix.

There is a so-called digital delay V4ff that writes to obtain the desired delay. FIG. 2 is a block diagram showing an example of a conventional digital delay device. In FIG. The unit delay (minimum delay width) in this digital delay III is equal to one cycle of the basic tarock φ. The basic output clock φs inputted from the input terminal 1 is given to the address counter 2. This address counter 2 is incremented at the rising edge of the basic clock φ, and
It outputs the X address to the decoder 3 and the Y address to the Y decoder 4. Input terminal 13. ~13. is the basic clock φ
This is a terminal that receives an input data signal that is input in synchronization with s, and will be described here with a configuration that receives n-pit input.

The MSB (R upper pit) of the input data signal is connected to terminal 13.
, the LSB (lowest pit) is connected to terminal 13. shall be given to. The input data signal is applied via input latch 11 to a write circuit controlled by signal @WE. The memory cell array 5 is a group of memory cells arranged in a matrix, and has a storage capacity of M×n bits. Transfer gate 6 transmits read data from memory cell array 5 to sense amplifier 7, and also transmits data from write circuit 10 to memory cell array 5. The sense amplifier 7 is controlled by the signal SE and amplifies the read data. The data latch 8 temporarily stores the output of the sense amplifier 7. While the signal SE is at a low level, the data latch 8 amplifies the read data. The output latch 9 outputs the delayed output from the data latch 8 in the cycle of the basic tarlock φs, and outputs the delayed output from the data latch 8 at the output terminals 12. to 1.
2. give to The MSB of the output data signal is at terminal 12. , the LSB is connected to terminal 12. Output from l.

Further, the basic clock φ which is input from the input terminal 1 is given to the timing generator 14 .

This timing generator 14 divides the basic clock φf and generates a signal SE and a signal WE in the timing sequence shown in FIG. The signal SE puts the sense amplifier 7 into an active state during a high level period, and the signal WE puts a write circuit 8 into an active state during a high level period. Note that the address counter 2 is reset to M by a reset circuit (not shown).
Reset every cycle. The conventional digital delay device is configured as described above.

In PAL television reception, an analog video signal is sampled at a frequency of 4rsc (rsc: color subcarrier frequency) to generate a digital video signal, and a delay of one scanning line (1Hil delay) is required to generate a digital video signal and perform digital processing. ) to realize a 1-line memory with the configuration shown in Figure 2, it becomes M-1135, n-8. Also, the X address is Xo -Xt, the Y address is Ya -Yz, and m locks φ One cycle of wealth is 5
It becomes 6ns.

Next, the operation of the conventional configuration example shown in FIG. 2 will be explained using the timing chart of FIG. 3. In this example, A,
A manner in which a delay of M cycles is obtained using an Mxn pit memory that has an address space of ~AM and processes data of n pits in parallel will be explained. In the memory used in this digital delay device, n arrays each having an address capacity of M are arranged, and one memory cell corresponds to each array for one address. Therefore, if an address consisting of n is specified, a total of n
memory cells are accessed in parallel. In a so-called byte-structured memory, the number is n-8. In the following explanation, the input data newly stored at each address of A and ~A- will be referred to as D and ~DM, respectively, and the output data read from A and ~An will be referred to as PD and ~PDM, respectively. shall be.

First, the address counter 2 is operated by the basic clock φ and outputs an X address to the X decoder 3 and a Y address to the Y decoder 4.

The X decoder 3 selects a row of n array addresses in the memory cell array 5, and the information of the memory cells belonging to that row is given to the transfer gate 6. In the transfer gate 6, a column is selected by the Y decoder 4 among the memory cells in the 0th row read from the memory cell 7 ray 5, and the data of the memory cells with a total of n pits belonging to the selected column are transferred to the I10 line 17. is output to. For example, if the output of address counter 2 specifies address A,
Information PD of a total of one memory cell located at each address A of the n arrays is read out in parallel via the transfer gate 6. The n-pit data PD, which is successively outputted, is amplified by the sense amplifier 7 while the signal MSE is at a high level, and is taken into the data latch 8. Signal S
As the signal SE falls, the data latch 8 is electrically disconnected from the sense amplifier 7, so that the data latch 8 then stores the read data PD while the signal SE is at a low level.

hold. Read data PD is transmitted to output latch 9 and output to n output terminals 121-12. These are output in parallel. In this way, as shown in FIG.
In response to changes in the address signal for each cycle of the cloud,
Data is read out sequentially.

On the other hand, during the specified period of the same address after the signal SE falls, the write circuit 10 operates during the high level period of the signal WE and transfers the n-pit input signal sent from the input latch 11 to I10. The data is transmitted to line 17 to rewrite the data in the selected memory cell. For example, address A,
Immediately after the previous data PD+ is read and stored in the data latch 8, new data O1 is written into the memory cell at address A. Data D is read out when address A+ is designated again after M cycles. In this way, for the memory cell at each address, READ-MODIFIEO-WRIT is performed every M cycles.
When the E operation is completed, the newly written data is output after M cycles, and a delay of M cycles can be realized.

[Problems to be Solved by the Invention] As explained above, the conventional digital delay device must perform reading and writing during one cycle of the basic tarlock φs. Therefore, the read access time until data latch and the 8-inclusion completion time (pulse width of signal WE)
The cycle of the basic clock φs must be determined by taking into consideration the pulse width of the signal Sε, the timing margin between address signals, etc., which poses problems such as making it difficult to increase the speed. . For example, the digital delay used in PAL television receivers!
A cycle time of 56 ns is required for f, but if the above conventional configuration is adopted using conventional process technology, READ-MOD r F I ED is completed within 55 ns.
-WRITE! However, it was difficult to operate with sufficient timing margin.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a digital delay device that is faster than the conventional configuration using the same process technology as the conventional one.

[Means for solving m points between points] The digital delay device according to this invention divides the address space of a group of memory cells arranged in a matrix into halves, and the memory cells in each divided address space are basically READ-MOD in twice the cycle of clock pulse
iFIED-WRITE is completed, and the two address spaces are alternately accessed with a phase shift of one cycle of the basic clock pulse, and read data from both address spaces are alternately accessed at the clock rate of the basic clock pulse. While being output, input data that is input in synchronization with the basic clock pulse is alternately entered into both address spaces three times.

[Operation] In this invention, while each address space is substantially operated at a clock rate equivalent to two cycles of the basic clock pulse, the data input/output operation is apparently completed in the same cycle as the basic clock pulse. Therefore, the digital delay device can be operated at a clock rate of half the minimum operation cycle of each address space, and high-speed performance can be obtained.

[Embodiments of the invention] FIG. 1 is a block diagram showing one embodiment of the present invention.

The digital delay device shown in FIG. 1 is for realizing a delay of M cycles for n-pit input data.The memory cell array is divided into two, and the first memory cell array 84 is arranged on an even address plane. form the second
The memory cell arrays form an odd address plane, and each memory cell array has an equal storage capacity of (M/2)Xn pits. A basic clock φs is input to the input terminal 80, and one cycle of the basic clock φS is equal to a unit delay. Terminal 101. ~101. is a terminal for receiving an n-pit input data signal input at the clock rate of the basic clock φ5, and the input data signal is applied to the write circuit 88.98 via the input latch 90. The timing generator 99 basically receives various timing signals φEV+φOD*5Etv, 5Eoo, WEtv in response to Otsukφs.
.

WEo o *OEE v and OEo o are generated in the timing sequence shown in FIG. Signal φEV
is the frequency of the basic clock φ, which is the basic clock φ
It has twice as many cycles as the fog, and the address counter 81 is incremented on its falling edge. The signal φ0 is a clock having the opposite phase of the signal φEV, and the address counter 91 is incremented at its falling edge. Faith @
5EEV, SE. . activate the sense amplifiers 86 and 96, respectively, during the high level period. Signal W
E Ev and WEoo respectively during the high level period,
The write circuits 88 and 98 are activated. Signal 0E(V controls the output of data latch 87, and signal 0Eoo controls the output of data latch 97.

The address counter 81 receives the signal φEV and supplies an even-numbered address to the X decoder 82 and an even-numbered Y address to the Y decoder 83 in the cycle of this signal φ(V (twice the cycle of the basic tarock Nakatomi). The output of the X decoder 82 is applied to the first memory cell array 84, and the output of the Y decoder 83 is applied to the transfer gate 85.Similarly, the address counter 91 receives the signal φ00 and calculates the cycle (basic) of the signal φoO. The X decoder 92 is supplied with an odd-numbered address, and the Y-decoder 93 is supplied with an odd-numbered Y address in cycles (twice the cycle of the clock φs).

The output of the X decoder 92 is applied to a second memory cell array 94, and the output of the Y decoder 93 is applied to a transfer gate 95. The transfer gate 85 is connected to the first memory cell array 8
4 is transmitted to the sense amplifier 86 via the I10 line 102, and data from the internal response circuit 88 sent via the I10 line 102 is transmitted to the first memory cell array 84. Similarly, transfer gate 95
is the read data from the second memory cell array 94! 1
The write circuit 9 is transmitted to the sense amplifier 96 via the 0 line 103 and is also sent via the I10 line 103.
8 is transmitted to the second memory cell array 94. The sense amplifier 86 is controlled by the signal SEE master,
The read data is amplified and provided to the data latch 87.

Data latch 87 temporarily stores the output of sense amplifier 86. When the signal 5EEV is at a low level, the data latch 87 is electrically isolated from the sense amplifier 86. Further, the data in the data latch 87 is transmitted to the output latch 89 while the signal OEgv is at a high level. Similarly, sense amplifier 96
is signal SE. . The read data is amplified and provided to the data latch 97 under the control of the control circuit. Data latch 97 temporarily stores the output of sense amplifier 96. When the signal 5Eoo is low level, the data latch 97 is connected to the sense amplifier 9.
It is configured to be electrically disconnected from 6. Also,
The data in the data latch 97 is transmitted to the output latch 89 while the signal 0'Eoo is at a high level. The eight output latches output M-cycle delayed outputs in synchronization with the basic clock φ atmosphere, and the output terminals 100. ~100o
give to Note that the address counters 81 and 91 each have a reset circuit (not shown), and are reset every M cycles. As described above, a digital delay device according to an embodiment of the present invention is configured.

FIG. 4 is a time chart for explaining the operation of the embodiment shown in the first factor. Next, referring to this figure 4,
The operation of the embodiment shown in the figure will be explained. In the following explanation, the input data input to the input latch 11 from the input terminals 101, ~101, and newly stored at the addresses A, ~AM will be referred to as gates D, ~D, respectively, and the addresses A, ~101, Let the output data read from ~AM be PD and ~PDM, respectively. A timing generator 99 divides the basic clock φ and generates a signal φEV and a signal φOD having the opposite phase. In response to the signal φ[■, the address counter 81 generates an even address Adtv of twice the cycle of the basic clock φs, and sends the X address of the number address to the X decoder 82 and the Y address of the even number address to the Y decoder 83. Output. On the other hand, in response to the signal φOQ, the address counter 91 generates an odd address Adoo of twice the cycle of the basic clock φs, and sends an odd numbered X address to the X decoder 92 and an odd numbered Y address to the Y decoder 93. Output. What should be noted here is that even address Ad (v and odd address Ado
o means that the phase is shifted by one cycle of the basic clock φs. Now, in the first memory cell array 84, if the output of the address counter 81 specifies address A2, the memory cell nli located at address A is accessed by the X decoder 82 and Y decoder 83, and has already been accessed (M -1) n stored before cycle
The pit data P D 2 passes through the transfer gate 85 and is transferred to I1.
0 line 102. Data PD2 is signal 5E
While EV is at a high level, it is amplified by the sense amplifier 86 and taken into the data latch 87. Signal SEgv
At the falling edge of the data latch 87, the sense amplifier 8
Since it is electrically disconnected from 6, the imitation signal SE! However, during the low level period, the data latch 87 is read data PD2.
hold. The data PDz held in the data latch 87 is transmitted to the output latch 89 during the high level period of the signal OEV, and is transmitted to the output terminal 100 of the nfl. ~100
Data PDz is output from n. On the other hand, the signal WEεV
During the high level period, the write circuit 88 operates, and the new n-pit data D2 input from the input terminals 101 to 101o and stored in the input latch 90 is written into the memory cell at the same address A2. Thus, READ-MODIFIED-WRI in A2 address cycle
TE is completed.

1 of the basic clock φ$ from the start of the A2 address cycle
After a cycle has elapsed, the second memory cell array 94
Now A, the address cycle begins. The output of address counter 91 is address A.

is specified, n memory cells located at address As are accessed by X decoder 92 and Y decoder 93,
The n-pit data (PDs) already stored (M-1) cycles ago is read out to the I10 line 103 via the transfer gate 95.

Data PD is amplified by the sense amplifier 96 while the signal 5Eoo is at a high level, and is taken into the data latch 97. As the signal 5Eoo falls, the data latch 97 is electrically disconnected from the sense amplifier 96, so that the signal SEo is then applied.

While P is at low level, the data latch 97 holds the read data P.
Next, when the signal 0Eoo becomes high level, the data PD is transmitted to the output latch 89.
n output terminals 100. It is output from ~10°. On the other hand, the write circuit 98 operates during the high level period of the signal WEoo, and the input terminals 101, . The new n-pit data O input from and stored in the input latch 90
, are written to the same memory cell A. In this way, A
, 6 in the address cycle REA()-MO[)1F
The IED-WRITE operation is completed. During this period, when one cycle of the basic clock φs has elapsed from the start of the address cycle of A, the second memory cell array 84
Then, the A4 address cycle starts, and the data PD,
A read operation is being performed.

As a result of the above, the input data inputted at the clock rate of φS is written alternately to the first memory cell array 84 and the second memory cell array 94, and simultaneously to the output terminals 100 to 100. From the time when the read data from both memory cell arrays 84 and 94 is inputted, M cycles of the basic clock φs are taken from the memory cell arrays 84 and 94, and the read data is outputted alternately at the clock rate of the basic tarlock φs. In this way, each digital delay amount realizes an M-cycle delay.

In the above embodiment, the signals OEE v and OEo o are used to control the output of the data latch, but the signals φEV+φ00 may be used instead. In addition, the signals WEεv and WEoo are converted into the signals SEo o
, SEE v may be substituted. Roughly speaking, in the above embodiment, the signal 5EEV is activated during the first half period (one cycle of the basic clock φs) of the even address cycle, and the signal 5EEV is activated during the second half period (one cycle of the basic clock φs).
signal WEEV is activated, but signal SEεV remains active.

Both WEEV may be activated during the latter half of the even address cycle. In short, READ-MOD I F I E-WRITE during gq number address cycle
It is sufficient if the operation is completed. This corresponds to signals 5Eoo, WE in odd address cycles.

The same applies to O.

Roughly speaking, the above examples are the same! In order to access two memory cell arrays with an address space of 2 memory capacity, it was possible to obtain a data delay of an even multiple of the unit delay, but in order to obtain a data delay of an odd multiple of the unit delay, it is necessary to For example, one stage of delay circuit (register) may be provided.

Further, the digital delay device according to the present invention may be implemented using a static memory circuit or a dynamic memory circuit.

[Effects of the Invention] As described above, according to the present invention, the address space corresponding to the amount of delay is divided into two memory cell arrays, and in each memory cell array, the address space corresponding to the amount of delay is divided into two memory cell arrays. READ-MODIFI
The ED-WRITE operation is performed, and the address cycle phase is shifted by one cycle of the basic clock pulse φs between both arrays, and the read data from both arrays are alternately read at the clock rate of the basic tally clock pulse φS. At the same time, the input data input at the clock rate of the basic clock pulse φs is stored alternately in both arrays, so in reality, each array is input at the clock rate of two cycles of the basic clock pulse φs. While operating, the apparent basic clock pulse φ
Since data input/output operations can be completed at a rate of less than 2 seconds, the digital delay device can be operated at a clock rate equivalent to half the minimum operating cycle of the memory cell array, which is 2 times faster than conventional digital delay devices. This has the effect of providing twice the high-speed performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing an example of a conventional digital delay device. FIG. 3 is a time chart for explaining the operation of the conventional digital delay device shown in FIG. FIG. 4 is a time chart for explaining the operation of the embodiment of the present invention shown in FIG. In the figure, 81 and 91 are address counters, 82
and 92 are X decoders, 83g5 and 93 are Y decoders, 84 is a first memory cell array, 94 is a second memory cell array, 85 and 95 are transfer gates, 86 and 96 are sense amplifiers, 87 and 97 are data latches, 88 and 98 are write circuits, 89 and 90 are input latches, 99 is a timing generator, 100. ~10
0° is the output terminal, 101. ~101. l indicates an input terminal. Agent Masu Oiwac
++ 1~ Kasasa---! '1 Kukuku---
-Rishin 4th hand, continuation Kawa 1 Tadashi 112 (spontaneous) Mr. Commissioner of the Japan Patent Office ・-゛no I, Indication of the case Patent application No. 1983 264738+j
2. Title of the invention Digicle delay device 3. Person making the amendment 5. Details subject to amendment. Detailed explanation of the old invention IIt3 and Figure 1 of the drawings 6.1 Positive contents (1) Specification page 5 In line 11, "divide by r" is corrected to "receive". (2) Mei II also corrects page 7, lines 8 to 14 to the following sentence. In the memory cell array 5, among the cells belonging to the row selected by the X decoder 3, data of a total of n pits of memory cells in the column transferred to the transfer gate 6 selected by the Y decoder 4 is I( 3) Details! Correct "period output" on page 14, line 13 to "period, output". (4) Correct “Memory Cell Array” on page 16, line 13 of the Memorandum of Understanding to “Memory Cell Array J.” (5) Correct Figure 1 of the drawings as in the first cause attached to the separate ta.

Claims (1)

[Claims] The operation is controlled in synchronization with the basic clock pulse φ_s,
and a digital delay device that delays an input signal by a predetermined time width and outputs the delayed signal, comprising: an input terminal to which an input signal synchronized with the basic clock pulse φ_s is applied; and an even address having twice the cycle of the basic clock pulse φ_s. an even address signal generating means for generating a signal, having a cycle twice as long as the basic clock pulse φ_s, and having a cycle equal to or less than the basic clock pulse φ_s,
Odd address signal generation means for generating odd address signals having a phase difference by one cycle of s; a first memory cell array having an even address space and addressed by the even address signal; a second memory cell array having an odd address space and addressed by the odd address signal; and temporarily storing data in the first memory cell array addressed and read by the even address signal. and after the data of the first memory cell array is stored and held by the first latch means, the memory cell of the first memory cell array designated by the even number address signal at that time is a first data writing means for writing an input signal from the input terminal; and a second latch for temporarily storing and holding data of the second memory cell array addressed and read by the odd address signal. and after the data of the second memory cell array is stored and held by the second latch means, a memory cell of the second memory cell array designated by the odd address signal at that time is inputted from the input terminal. A digital device comprising: second data writing means for writing an input signal; and means for alternately outputting the data stored and held in the first and second latch means at the clock rate of the basic clock pulse φ_s. delay device.