JPS56163594A - Memory control device - Google Patents

Memory control device

Info

Publication number
JPS56163594A
JPS56163594A JP6444280A JP6444280A JPS56163594A JP S56163594 A JPS56163594 A JP S56163594A JP 6444280 A JP6444280 A JP 6444280A JP 6444280 A JP6444280 A JP 6444280A JP S56163594 A JPS56163594 A JP S56163594A
Authority
JP
Japan
Prior art keywords
address
memory
memories
written
lowest
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6444280A
Other languages
Japanese (ja)
Inventor
Takashi Minagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP6444280A priority Critical patent/JPS56163594A/en
Publication of JPS56163594A publication Critical patent/JPS56163594A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To realize a read/write with every 16 bits from an odd address for a 16-bit processor, by dividing a memory into two parts and then exchanging the read/write data between the 1st and 2nd memory sections. CONSTITUTION:When the data ''3456'' is written into an odd address (0001)16 of a memory ''34'' and ''56'' are written into exchangers 6 and 7 respectively via a bus 8. The address (0001)16 is stored in an address latch 3. As the lowest digit of the address is (1)16, i.e., an odd number, a cross connecton is secured between the exchangers 6/7 and the memories 2/1 and the contents ''34'' and ''56'' are supplied to the memories 2 and 1 respectively. The contents (0001)16 of the latch 3 receives an addition through a counter to be (0002)16. The lowest digits of (0001)16 and (0002)16 are (1)16 and (2)16 respectively to be turned into (0001)2 and (0010)2 in the form of a binary display. However, the lowest bit of the lowest digit of an address is not used for selection of the memories 1 and 2, (0001)2 and (0010)2 are shown as (000)2=(0)16 and (001)2=(1)16 respectively. The addresses which are applied to the memories 1 and 2 are (0001) 16 and (0000)16 each. Accordingly ''34'' and ''56'' are written into the address (0000)16 of memory 2 and the address (0001)16 of memory 1 respectively.
JP6444280A 1980-05-15 1980-05-15 Memory control device Pending JPS56163594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6444280A JPS56163594A (en) 1980-05-15 1980-05-15 Memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6444280A JPS56163594A (en) 1980-05-15 1980-05-15 Memory control device

Publications (1)

Publication Number Publication Date
JPS56163594A true JPS56163594A (en) 1981-12-16

Family

ID=13258388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6444280A Pending JPS56163594A (en) 1980-05-15 1980-05-15 Memory control device

Country Status (1)

Country Link
JP (1) JPS56163594A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61142814A (en) * 1984-12-14 1986-06-30 Mitsubishi Electric Corp Digital delay device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61142814A (en) * 1984-12-14 1986-06-30 Mitsubishi Electric Corp Digital delay device
JPH0159766B2 (en) * 1984-12-14 1989-12-19 Mitsubishi Electric Corp

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