JPS5715271A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5715271A
JPS5715271A JP8878980A JP8878980A JPS5715271A JP S5715271 A JPS5715271 A JP S5715271A JP 8878980 A JP8878980 A JP 8878980A JP 8878980 A JP8878980 A JP 8878980A JP S5715271 A JPS5715271 A JP S5715271A
Authority
JP
Japan
Prior art keywords
memory
significant digit
address
numbered
digit bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8878980A
Other languages
Japanese (ja)
Inventor
Kenichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8878980A priority Critical patent/JPS5715271A/en
Publication of JPS5715271A publication Critical patent/JPS5715271A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To obtain access to continuous contents once without reference to whether the addresses are even-numbered or odd-numbered, by settting a memory address except the least-significant digit bit in an address counter which counts and updates its contents according to the information of the least-significant digit bit of a register. CONSTITUTION:The memory device is provided with a memory consisting of memories 4 and 5 for even and odd addresses, an address register 2 holding its memory address and giving a memory address excluding its least-significant digit bit to the memory 5, and an address counter 3 wherein the memory address exlcluding the least-significant digit bit is set and whose count contents are updated according to information of the least-significant digit bit of the register 2. Consequently, access to the continuous content of the memory is completed by the simple constitution regardless of whether memory address are even-numbered or odd-numbered, thus increasing an access speed.
JP8878980A 1980-06-30 1980-06-30 Memory device Pending JPS5715271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8878980A JPS5715271A (en) 1980-06-30 1980-06-30 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8878980A JPS5715271A (en) 1980-06-30 1980-06-30 Memory device

Publications (1)

Publication Number Publication Date
JPS5715271A true JPS5715271A (en) 1982-01-26

Family

ID=13952599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8878980A Pending JPS5715271A (en) 1980-06-30 1980-06-30 Memory device

Country Status (1)

Country Link
JP (1) JPS5715271A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167137A (en) * 1984-09-10 1986-04-07 Hitachi Ltd Microprogram control system
US5261073A (en) * 1989-05-05 1993-11-09 Wang Laboratories, Inc. Method and apparatus for providing memory system status signals
US5307469A (en) * 1989-05-05 1994-04-26 Wang Laboratories, Inc. Multiple mode memory module
US5327391A (en) * 1991-04-11 1994-07-05 Nec Corporation Double buffer type elastic store comprising a pair of data memory blocks
EP0607942A2 (en) * 1993-01-19 1994-07-27 Kabushiki Kaisha Toshiba Read only memory
US5479393A (en) * 1993-06-19 1995-12-26 Samsung Electronics Co., Ltd. Video ram having an option of a full sam and a half sam
US6452825B1 (en) * 1997-05-30 2002-09-17 Micron Technology, Inc. 256 meg dynamic random access memory having a programmable multiplexor
US6564308B2 (en) 1989-05-05 2003-05-13 Samsung Electronics Co. Ltd. Multiple mode memory module

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167137A (en) * 1984-09-10 1986-04-07 Hitachi Ltd Microprogram control system
US5261073A (en) * 1989-05-05 1993-11-09 Wang Laboratories, Inc. Method and apparatus for providing memory system status signals
US5307469A (en) * 1989-05-05 1994-04-26 Wang Laboratories, Inc. Multiple mode memory module
US6021477A (en) * 1989-05-05 2000-02-01 Samsung Electronics Co., Ltd Multiple mode memory module
US6499093B2 (en) * 1989-05-05 2002-12-24 Samsung Electronics Co., Ltd. Multiple mode memory module
US6564308B2 (en) 1989-05-05 2003-05-13 Samsung Electronics Co. Ltd. Multiple mode memory module
US5327391A (en) * 1991-04-11 1994-07-05 Nec Corporation Double buffer type elastic store comprising a pair of data memory blocks
EP0607942A2 (en) * 1993-01-19 1994-07-27 Kabushiki Kaisha Toshiba Read only memory
EP0607942A3 (en) * 1993-01-19 1994-08-24 Toshiba Kk Read only memory.
US5479393A (en) * 1993-06-19 1995-12-26 Samsung Electronics Co., Ltd. Video ram having an option of a full sam and a half sam
US6452825B1 (en) * 1997-05-30 2002-09-17 Micron Technology, Inc. 256 meg dynamic random access memory having a programmable multiplexor

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