JPS5474640A - Channel unit - Google Patents

Channel unit

Info

Publication number
JPS5474640A
JPS5474640A JP14164777A JP14164777A JPS5474640A JP S5474640 A JPS5474640 A JP S5474640A JP 14164777 A JP14164777 A JP 14164777A JP 14164777 A JP14164777 A JP 14164777A JP S5474640 A JPS5474640 A JP S5474640A
Authority
JP
Japan
Prior art keywords
gate
data
flag
register
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14164777A
Other languages
Japanese (ja)
Inventor
Takeshi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14164777A priority Critical patent/JPS5474640A/en
Publication of JPS5474640A publication Critical patent/JPS5474640A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perfrom transfer from the buffer memory to the main memory, by identifying the final data transferred from the input device with FF and setting the flag FF, in the buffer memory control section for channel.
CONSTITUTION: The end of data transfer is detectd with FF30, and FF 60 is set at the same time when the data is latched to the ID register 02 with the delivery signal S1 delivered. The output passes through the OR gate 71 and sets the flag 10 or 11 corresponding via the AND gate 70 designated with the upper rank 1 bit of the B address counter 20. Thus, by only using one FF and AND gate, the address memorizing register for the first data and the comparison circuit in conventional channel units can be made unnecessary.
COPYRIGHT: (C)1979,JPO&Japio
JP14164777A 1977-11-28 1977-11-28 Channel unit Pending JPS5474640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14164777A JPS5474640A (en) 1977-11-28 1977-11-28 Channel unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14164777A JPS5474640A (en) 1977-11-28 1977-11-28 Channel unit

Publications (1)

Publication Number Publication Date
JPS5474640A true JPS5474640A (en) 1979-06-14

Family

ID=15296900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14164777A Pending JPS5474640A (en) 1977-11-28 1977-11-28 Channel unit

Country Status (1)

Country Link
JP (1) JPS5474640A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621220A (en) * 1979-07-30 1981-02-27 Ibm Data interface mechanism
JPS56116139A (en) * 1980-02-18 1981-09-11 Fujitsu Ltd Production system of transfer data quantity
JPS59721A (en) * 1982-06-28 1984-01-05 Panafacom Ltd Control system of information transfer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621220A (en) * 1979-07-30 1981-02-27 Ibm Data interface mechanism
JPS5757739B2 (en) * 1979-07-30 1982-12-06 Intaanashonaru Bijinesu Mashiinzu Corp
JPS56116139A (en) * 1980-02-18 1981-09-11 Fujitsu Ltd Production system of transfer data quantity
JPH0133848B2 (en) * 1980-02-18 1989-07-17 Fujitsu Ltd
JPS59721A (en) * 1982-06-28 1984-01-05 Panafacom Ltd Control system of information transfer

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