SU1368914A1 - Apparatus for magnetic recording of asynchronous signals - Google Patents

Description

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By the information inputs to the information outputs of the first counter, connected to the second group of information inputs of the first comparison unit, the first group of information inputs of the second comparison unit is connected to the information outputs of the second register connected by a synchronized input with the output of the second element NOT-OR and under the connected information inputs to the outputs of the second counter, connected to the second group of information inputs of the second comparator unit, and the second one-shot is equipped with a bus connected to its input power supply voltage and is connected to the output

the first input of the second element NOT-OR connected by the second input to the output of the NAND element to the reset input of the first trigger, to the synchronization input of the second counter, connected by information inputs to the outputs of the original number setting signal generator, and to the input of the third one-oscillator connected output with the second setup input of the second trigger and the second input of the first element NOT-OR, the output of which is connected to the reset inputs of the first and second counters connected by counting inputs respectively to the first and the second information outputs of the multiplexer.

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The invention relates to the field of accumulation of information, namely, devices for magnetic recording of asynchronous signals.

The purpose of the invention is to reduce the distortion of the magnetic recording of asynchronous signals.

FIG. 1 and 2 depict one of the possible variants of the proposed device for magnetic recording of asynchronous signals.

The device contains a driver 1 information signals connected by an input to the information bus 2, a recording amplifier 3 connected by an output to a magnetic head 4, a driver of 5 clock pulses, a sawtooth voltage generator 6 detector 7, a controlled generator 8 and the first and second buffer accumulators 9 and 10, the Shaper 5 clock pulses are connected by an input to the input bus 11 of the clock signal and connected by output 12 to the control input of the sawtooth generator 6, the output of which through the detector 7 is connected to the input m controlled generator 8.

The device also contains a multiplexer 13 connected by the first and second information outputs to the inputs for selecting the first and second buffer drives 9, respectively.

and 10, connected by information inputs with outputs 14 of driver 1 of information signals, bus driver 15, first and second counters 16 and 17, first and second triggers 18 and 19, AND-NOT element 20, element 21, first, second and third one-shot 22, 23 and 24, the first and second elements NOT-OR 25 and 26 the first and second blocks 27 and 28 of the comparison, the first and second registers 29 and 30 and the shaper 31 of the initial number setting signals. Bus driver 15 is connected by information outputs to inputs 32 of recording amplifier 3 connected to output 33 of controlled generator 8, first and second counters 16 and 17 are connected by information outputs to address inputs of first and second buffer stores 9 and 10, respectively. Direct output of first trigger 19 is connected to the first input of the NAND 20 element, to the write and read inputs of the first buffer accumulator 9 and to the control input of a multiplexer 13 connected by information inputs to the output 33 of the controlled oscillator 8, outputs of the first and second blocks 27 and 28 of comparator 12 and output clock pulse shaper 5. Exit 12 formatiruvatel 5 clock pulses under

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keys to the second input of the element AND-NOT 20 and to the first input of the element AND 21 connected by the second input to the inverse output of the first trigger 18 connected to the write and read inputs of the second buffer storage unit 10. The third information output of the multiplexer 13 is connected to the input of the first one-oscillator 22, the output of which is connected to the counting input of the first trigger 18, to the first input of the first element NOT-OR 25 and to the first installation input of the second trigger 19. The direct output of the second trigger 19 is connected to the input selector bus driver 15, pos single information inputs to the information outputs of the first and second buffer accumulators 9 and 10. The first group of information inputs of the first comparison block 27 is connected to information outputs of the first register 29 connected by a synchronization input from the output of the And 21 element and the connected information inputs to the information outputs of the first counter 16, connected to the second group of information inputs of the first comparison unit 27. The first group of information inputs of the second comparison unit 28 is connected to the information outputs of the second register 30 connected by a synchronization input to the output of the second element NOT-OR 26 and connected by information inputs to the outputs of the second counter 17 connected to the second group of information inputs of the second comparison unit 28. The second one-shot 23 is provided with a supply voltage supply 34 connected to its input and connected by an output to a first input of a second element NOT-OR 26 connected by a second input to an output of element IS-NOT 20 to a reset input of the first trigger 18, to the clock input of the second counter 17, connected infor

35 in-50 output terminals with outputs for 3 recording amplifier and

the peacemaker 31 sets the initial number, and to the input of the third one-shot 24. The output of the third one-shot 24 is connected to the second setting input of the second trigger 19 and to the second input of the Lervogr NOT-OR element 25, connected by the output to the reset inputs of the first and second counters 16 and 17 which are subconnected 13. "

When the supply voltage appears on the supply voltage bus 34, the second one-oscillator 23 generates a first-order initial impulse, setting the first trigger 18 to the zero state, and the second counter 17 to the state set by the setter 31.

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0

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yen counting inputs, respectively, to the first and second information outputs of the multiplexer 13.

The output 33 of the controlled oscillator B is connected to the input of the rotation signal generator 36, the output of which is connected to an electric motor 37 mounted with the possibility of moving a magnetic recording medium. In so doing, the control input of the rotation signal generator 36 is connected to the electric motor 37.

Multiplexer 13, first and second 5 buffer drives 9 and 10, bus driver 15, first and second counters 16 and 17, first and second triggers 18 and 19, AND-NOT element 20, And 21 element, first, second and third one-shot 22 , 23 and 24, the first and second elements NON-OR 25 and 26, the first and second blocks 27 and 28 of the comparison, the first and second registers 29 and 30 are part of the compensator 38 of detonations.

Magnetic recording of asynchronous signals through the proposed device is as follows.

The sync signal is fed through the input bus 11 of the sync signal to the driver of 5 clock pulses, which starts the generator 6 of the sawtooth voltage. In this case, the amplitude of the sawtooth voltage of the generator 6 sawtooth voltage is proportional to the period of the clock pulses of the driver 5 clock pulses. The sawtooth voltage generator 6 through the detector 7 acts on the controlled generator 8, producing pulses, the frequency of which is proportional to the average frequency of the clock of the pulse generator of the clock generator 5. The pulses of the controlled oscillator 8 are fed to the rotation signal shaper 36, which provides rotation of the electric motor 37. In addition, the pulses of the controlled oscillator 8 are 0 and 0

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multigaxor 13. "

When the supply voltage appears on the supply voltage bus 34, the second one-shot 23 produces a first pulse of the initial setup, setting the first trigger 18 to the zero state, and the second counter 17 to the state set by the driver 31 of the setup signals

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source number. The first impulse of the initial installation through the second element NOT-OR 26 sets the second register 30 to a state similar to that of the second, counter 17.

On the falling edge of the first impulse of the initial installation, the third one-shot 24 produces a second impulse of the initial setting, which sets the second trigger 19 to the single state, and through the first element NOT-OR 25 resets the first and second counters to zero. and 17.

On the zero level from the direct output of the first trigger 18, multiplexer 13 connects the output 12 of the driver 5 clocks to the select input of the first buffer accumulator 9 and the counting input of the first counter 16, the output 33 of the controlled oscillator 8 to the select input of the second buffer accumulator 10 and to the counting input of the second counter 17, and the output of the second comparison unit 28 to the input of the first one-shot 22. The logic level O from the direct output of the first trigger 18 goes to the write and read inputs of the first buffer accumulator 9 and allows write, and also prohibits the arrival of clock pulses from the output 12 of the clock 5 clock pulses through the element IS-NOT 20 and the second element NOT-OR 26 to the clock input of the second register 30, the logic level 1 from the inverse output of the first trigger 18 allows the clock to pass from the output 12 generator 5 clock pulses through the element 21 to the clock input of the first register 29. In addition, the logic level -1 from the inverse output of the first trigger 18 is fed to the write and read inputs of the second buffer accumulate Ate 10, prohibiting writing to it and allowing the reading of it.

The logic level 1 from the direct output of the second flip-flop 19 prohibits the passage of the readout result through the bus driver 15 to the inputs 32 of the amplifier 3 write.

The information signals are received from the outputs 14 of the imaging unit 1 of the information signals to the information inputs of the first and second buffer drives 9 and 10 and are recorded in

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that one of them, at the entry of which is present the Level of logical O.,

After the initial setup, the clock signals from the output 12 of the clock clock generator 5 write information signals to the first buffer memory 9. At the same time, the back edges of the clock pulses switch the first counter 16, and write the address to the first register. .

The pulses from the output 33 of the controlled generator 8 pass to the input of the selection of the second buffer accumulator 10 and to the counting input of the second counter 17. These information pulses read information from the second buffer accumulator 10. However, the read information does not pass through the bus driver 15, since at its input of choice there is a prohibitive level of logical 1.

The second counter 17 switches over the back edges of the pulses from the output 33 of the controlled generator 8 after reading each successive word from the second buffer accumulator 10. Each next address is compared by the second comparison unit 28 with the address stored in the second register 30. When the addresses are compared, the second block 28 Comparison forms the logical level: 1, which enters the input of the first one-shot 22. The first one-shot 22 operates at the time of the disappearance of the level of logic 1 at its input at the end of the reading of the last word. The pulse of the first one-shot 22 switches the first and second triggers 18 and 19 to the single and zero states, respectively, and through the first non-OR 25 element resets the first and second counters 16 and 17 to the zero state.

After switching to the zero state, the second trigger 19 resolves the receipt of the read information from the first and second buffer accumulators 9 and 10 through the bus driver 15 to the inputs 32 of the write amplifier. The information pulses and pulses from the output 33 of the controlled oscillator 8 are transmitted through the recording amplifier 3 to the magnetic head 4, which ensures recording on the magnetic recording medium. In this case, in the first register

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29, the address of the last word recorded in the first buffer store 9 will remain fixed.

After switching the first trigger 18 to a single state, multiplexer 13 connects the output 12 of the clock generator 5 clock pulses to the select input of the second buffer accumulator 10 and the counting input of the second counter 17, the output 33 of the controlled oscillator 8 to the select input of the first buffer accumulator 9 and the counting input of the first counter 16, and the output of the first comparison unit 27 to the input of the first one-shot 22. In this case, the first

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and second buffer stores 9 and 10 change roles; Information is read from the first buffer accumulator 9, and information is written to the second buffer storage device. Writing to the second buffer drive 10 and reading it. The first buffer accumulator 9 is implemented in the same way as described in the first buffer accumulator 9 and reading from the second buffer accumulator 10. The recording is made until the end of reading after 15 the next storage word recorded in the first buffer accumulator 9 in the previous cycle.

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FIG. 2

Claims (1)

DEVICE FOR MAGNETIC RECORDING OF ASYNCHRONOUS SIGNALS, comprising an information signal shaper connected to the information bus by an input, a recording amplifier connected by an output to the magnetic head, a clock shaper connected by an input to the clock input bus and connected by an output to the control input of the sawtooth voltage generator, the detector is connected to the input of a controlled generator, and the first and second buffer drives, characterized in that, in order to reduce distortion magnetic recording of asynchronous signals, a multiplexer is inserted into it, connected by the first and second information outputs to the inputs of the selection of the first and second buffer drives, respectively, connected by information inputs to the outputs of the driver of information signals, a bus driver connected by information outputs to the inputs of a recording amplifier connected to the output controlled generator, the first and second counters connected by information outputs to the address inputs of the first and second, respectively buffer drives, the first and second triggers, the first and second comparison blocks, the H-NOT element, the AND element, the first, second, third one-shots, the first and second HE-OR elements, the first and second registers and the signal conditioning unit for setting the initial number, and direct the output of the first trigger is connected to the first input of the NAND element, to the recording and reading inputs of the first buffer storage device, and to the control input of the multiplexer, connected by information inputs to the output of the controlled generator, with the outputs of the first and second blocks f and with the output of the pulse shaper, the output of which is connected to the second input of the AND gate and to the first input of the AND gate connected to the second input with the inverse output of the first trigger connected to the write and read inputs of the second buffer filler, the third information output of the multiplexer is connected with the input of the first one-shot connected to the counting input of the first trigger, to the first input of the first HE-OR element and to the first installation input of the second trigger, the direct output of which is connected to the input om the choice of a bus driver connected to the information outputs of the first and second buffer drives by the information inputs, the first group of information inputs of the first comparison unit is connected to the information outputs of the first register, connected by the synchronizing input to the output of the And element and connected by information SU 1368914 to the information outputs of the first counter connected to the second group of information inputs of the first comparison unit, the first group of information inputs of the second unit the comparison is connected to the information outputs of the second register connected to the output of the second HE-OR element and connected by the information inputs to the outputs of the second counter connected to the second group of information inputs of the second comparison unit, and the second one-shot is equipped with a supply voltage bus connected to its input and connected by the output to the first input of the second HE-OR element, connected by the second input to the output of the AND-NOT element to the reset input of the first trigger, to the clock input in the second counter connected to the information inputs with the outputs of the signal generator for setting the initial number, and to the input of the third one-shot connected to the second installation input of the second trigger and the second input of the first HE-OR element, the output of which is connected to the reset inputs of the first and second counters connected counting inputs, respectively, to the first and second information outputs of the multiplexer.