SU949720A1 - Device for checking information recorded in storage units - Google Patents

Description

one

The invention relates to memory devices and can be used to monitor real-time memory devices.

A device for controlling the recording of information in memory blocks is known, which contains a drive, a number register, an address register, an address decoder with address formers, bit drivers, a reproduction amplifier block, a control information generating unit, two triggers and five logic elements 1.

The disadvantage of the device is the impossibility of self-control.

The closest technical solution to the invention is a device containing shapers of a write interval and a read end, AND elements and OR elements, whose inputs are connected respectively to the output of the write driver and the first And element, and the output is connected to the Write bus and through sequentially connected read drivers and the end of the readout - with the input of the second element And, the other input of which is connected to the output of the comparison circuit, and the output with the first inputs of the first and third elements And, the second inputs of which are connected respectively to the direct and inverse outputs of the imaging unit of the recording interval, the input of which is connected to the output of the recording imaging unit, and the output of the third element I is connected to the bus “Failure 2.

A disadvantage of this device is its low speed, since the signal at the output of the comparison circuit can cause re-recording at this address until the time-interval for the control has been removed for correction.

The purpose of the invention is to increase the speed when using to check the accuracy of the data recorded test readout.

The goal is achieved by the fact that 20 in the device for controlling the recording of information in the memory blocks, containing a comparison circuit whose inputs are the information and control inputs of the device, the main address register and the local control unit whose inputs are the control inputs of the device are entered additional address register, comm; iiaKOiiirrcJih and the first trigger,) l :. () iixo.i. KOTopoio is connected to R), ivfj,; .mig srainoni, synchronous input: i; iii n N-i-riiiiiCH ij of the n-mode synchronization regI ... ring and,) s () sync pulses 6l) -. MfcTHoio control, the output of the first trigger ;, is connected to the informational INPUT of the storage device whose address input is soy, 1, and the output of the additional registration address, whose informational input is connected to the output of the switch, the first, second, third and fourth inputs of which are connected respectively to output and with the address input of the main register of the address and with the control outputs of the local control unit, the recording control output of which is connected to the control input of the accumulator whose output is the information output of the device oystva. In addition, the local control unit contains the second, third and fourth triggers, the write pulse shaper, the OR-J1 element OR-NOT element and the NOT element, with the output of the OR-AND element connected to the synchronization input of the second trigger, the first input of the write pulse generator and element NOT, the output of which is connected to the synchronization input of the third trigger, the inverse output of which is connected to the second input of the write pulse former, the output of which is connected to the synchronization input of the fourth trigger, the setup input d which is connected to the information input of the first trigger and the first input of the element OR NOT, the second input of which is connected to the direct output of the second trigger, the installation and information inputs of the third fpHrrepa, the third input of the element OR NOT is connected to the inverse output of the fourth trigger and the first inputs of the element OR-I, the second inputs of which are connected to the forward output of the fourth trigger, the second reset input of which is combined with the reset input of the second trigger and is one of the block inputs, the information input of the second trigger, reti and fourth inputs of the OR-AND are respectively block other inputs, the outputs of OR-NO element and OR-AND write pulse shaper, a direct output of the fourth flip-flop and the second flip-flop outputs are the outputs. FIG. 1 shows a functional diagram of the proposed device; Fig. 2 is a functional diagram of the most preferred embodiment of the local control unit; in fig. 3 - timing charts of the device. The device contains the main register of 1 address. FIG. 1 shows a monitored memory block 2 performed on chips. The device also contains a switch 3, an additional address register 4, a drive 5 for storing check bits of information, a comparison circuit 6, a local control block 7 and a first trigger 8 for storing the comparison result for the time required to write them to storage device. The local control unit contains (Fig. 2) an OR-AND 9 element, a second trigger 10 for controlling the switch, an OR-NOT 11 element, a HE element 12, a third trigger 13 for generating an additional clock pulse, a write pulse driver 14 and a fourth trigger 15 for controlling read mode m. FIG. 1-3 depicts the read and write clock pulses 16, write pulses 18 from the local control unit, switch control pulses 19, pulses 20 at the output of the main address register, pulses 21 at the output of the additional address register, pulses 22 at the output of the write pulse generator, the pulses 23 at the input of the selection of the crystal of the memory unit, the additional sync pulse 24 at the inverse output of the third trigger, and the pulse 25 the read mode at the output of the fourth trigger. FIG. 3 denotes the addresses AO, AI, Aj, A4, AP with sequence numbers O, 1, (n-1), where n is an integer, and arbitrary addresses X, which are generated at the output of the main and additional address registers. The device works as follows. In the mode of recording the data array to the first control input of the unit 7 (Fig. 1) the logical 1 is supplied before the arrival of the clock pulses 17 (Fig. 3) of the recording to the second control input of the unit 7 (Fig. 1). The write pulse 18 (Fig. 3) switches trigger 15 (Fig. 2) and, by controlling the OR-AND element 9, connects to the synchronization inputs of registers 1 and 4 (Fig. 1), trigger 8 (Fig. 1), triggers 10 and 13 (FIG. 2) write sync pulses 17 (FIG. 3). The first of the synchronization pulses 17 records the switching of the trigger 10 according to the pulses 19 of the control switch taken from the direct and inverse outputs of the trigger 10, the information inputs of the register 4 are connected to the outputs of the register 1. As this switching occurs on the front of the clock 17 coming from the block 7, then on the first clock pulse 17 entries in registers 1 and 4

the same information will be recorded, the second clock pulse 17 in the register 1 will write the new address from the input of the device address, and register 4 will write the contents of register 1, i.e. the same as in register 4 after the first clock pulse.

According to the following clock pulses 17 records, the formation of addresses in both registers 1 and 4 occurs with a shift. The process of generating addresses during writing is shown in the time diagram (Fig. 3), where the AP is the address with the sequence number n, X is an arbitrary address.

Addresses 20 and 21 are formed on the front of the clock pulses 17 of the record. By their decay, the shaper 14 generates a pulse 22 which, falling on the inputs “Record-Read of block 2 and accumulator 5, causes the recording of information present on their information inputs at the corresponding addresses formed in registers I and 4. Pulse 18 is written from block 7 must end no later than t -f tgj + tjj. before the front of the next sync pulse arrives, where t is the delay time of the sync pulse front edge of the trigger 8 relative to the time the information appears at the information input of the trigger 8, recovery time in block 2 after recording, tec is the delay in comparison circuit 6. At the end of the write pulse 18, the device enters the read mode, i.e., after tea time after the end of the write pulse 18, the code recorded at the address contained in the register appears at the first input of the comparison circuit 6 1. At the second input of the comparison circuit 6, there is content received at the information input of the device. At a time tec, the output of the comparison circuit 6 appears: a logical "O, if the codes are both common, and a logical" 1, if the codes are different.

The comparison result is fed to the information input of the trigger 8. On the front of the following clock pulse 17, the comparison result is written to the trigger 8 and appears at the information input of the accumulator 5, whose address input contains the address rewritten from register 1 to register 4. The next pulse 18 of the write Unit 7 causes the comparison result to be written to drive 5 at the address that corresponds to the information monitored during the previous clock pulse 17.

The recording mode ends when a logical "O" is applied to the first control input of block 7 after the front of the sync pulse 17, corresponding to, for example, the last measurement, the results of which are recorded in block 2. Then, according to the following (additional) sync pulse 17, the trigger 10 has the state “O and switch 3 connects to the information input of the register 4 input device address. But in register 4, the previous state of register 1 will have time to be recorded, since both trigger 10 and registers 1 and 4 are triggered on the front of the sync pulse 17.

Switching to the state "About the front of the additional clock pulse, trigger 10 sends a logical" O to the input of the trigger trigger 13 and, thus, allows the trigger 13 to switch along the fall of the additional clock pulse. But at the same time, a pulse 22 will have time to form at the output of shaper 14, which is fed to the control inputs of the Write-Read block 2 and the accumulator 5, in which the result of the last check reading of information is recorded.

In order for the last pulse 22 not to record the information in block 2, in block 7 the prohibiting pulse 23 is formed using element ILINE 11; arriving at the chip select input of block 2. At the end of the pulse, 22 is set to "1 flip-flop 15 and, controlling the element OR-AND 9, connects the read clock to the clock inputs of register 1, flip-flop 8, flip-flops 10 and 13. The appearance of a logical" b on the third output (control) (read mode) of block 7 indicates the start of the read mode.

In read mode, the information inputs of registers 1 and 4 are connected to the input address of the device. Thus, the read sync pulses to the address inputs of block 2 and accumulator 5 are given the same, rather than offset, as in write mode, addresses at which the codes recorded in block 2 marked in the event of an incorrect write of the logical " 1 in the check discharge.

Thus, when using switch 3, register 4 and trigger 8, it becomes possible to offset the addresses of accumulator 5 relative to the addresses of block 2 when writing. This makes it possible to record one word in a time equal to the recording time plus the reading time leads to gain in speed compared to writing without shifting addresses.

The textile-eco-friendly advantage of the proposed device lies in its higher speed, in comparison with the known, speed.

Claims (2)

1. A device for controlling the recording of information in memory blocks, comprising a comparison circuit whose inputs are the information and control inputs of the device, the main address register and the local control unit whose inputs are the control inputs of the device, characterized in that increase the speed of the device, it contains an additional address register, switch, storage device and the first trigger, the information input of which is connected to the output of the comparison circuit, the synchronization input is connected to the synchronization inputs address registers and the clock output of the local control unit, the output of the first trigger is connected to the information input of the accumulator, the address input of which is connected to the output of the additional address register whose information input is connected to the switch output, the first, second, third and fourth inputs of which are connected respectively to the output and with the address input of the main register of the address and with the control outputs of the local control unit, the output of the address is which is connected to the control input of the accumulator bodies whose output is the information output of the device. 2. The device according to claim 1, characterized in that the local control unit contains the second, third and fourth triggers, the recording pulse shaper, the OR element - AND, the element OR-NOT and the element NOT, and the output of the element-OR-AND is connected to the input synchronization of the second trigger, the first input of the write pulse generator and the input of the element NOT, the output of which is connected to the synchronization input of the third trigger, the inverse output of which is connected to the second input of the recording pulse generator, the output of which is connected to the synchronization input of the fourth trigger, the setting input of which is connected to the information input the first trigger and the first input of the element OR NOT, the second input of which is connected to the direct output of the second trigger, the setup and information inputs ter its trigger, the third input of the YLI-NOT element is connected to the inverse output of the fourth trigger and the first inputs of the OR-I elements, the second inputs of which are connected to the forward output of the fourth trigger, the second reset input of which is combined with the reset input of the second trigger and is one of the inputs block, the information input of the second trigger, the third and fourth inputs of the OR-AND element are respectively the other inputs of the block, the outputs of the OR-NOT element, the OR-AND element and the write pulse driver, the fourth output of the fourth trigger and the output The dyad of the second trigger is the output of the block. Sources of information taken into account in the examination 1.Putintsev ND. Hardware control of managing digital computing machines. M., “Owls. Radio, 1966, p. 85-103. 2. USSR author's certificate No. 723675, cl. G 11 C 29/00, 1976 (prototype).  1/7 T / 5 1 FIG. 3 Figure 2 / "/ 7