SU1510013A1 - Self-check storage - Google Patents

Abstract

The invention relates to computing and can be used in the construction of storage devices based on them with built-in controls. The aim of the invention is to increase the reliability of the control. The goal is achieved by simulating on the memory elements of the memory block of such a digital automaton, which allows for the return of the state of the memory elements of the memory block to the original. The device comprises a memory unit 1, multiplexers 6, modulo-two adders 7, triggers 8, a switch 10, a counter 11, and a control unit 21. 3 il.

Description

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The invention relates to computing technology and can be used in the construction of storage devices with built-in controls.

The purpose of the invention is to increase the reliability of the control.

Figure 1 shows the functional diagram of the device; figure 2 is a functional diagram of the counter; FIG. 3 is a functional block diagram of the control unit.

The device contains (Fig. 1) a memory block 1, having information inputs 2, address inputs 3, a write-read control input 4 and information outputs 5, which are also information output devices of the device, multiplexers 6, adders 7 modulo two, triggers 8, information inputs 9, switch 10, counter 11, which has counting input 12, control input 13 k of outputs 14.

The adders 7 have inputs 15 and 16 and outputs 17. The device also contains address inputs 18 and recording resolution input 19, first operating mode setting input 20, control unit 21 having inputs 22-24 and outputs 25-28.

The counter 11 (figure 2) contains a reversible counter 29, the trigger 30, the elements And 31 and 32, the element IL 33 and the element 34.

The control unit 21 contains (fig. 3) the triggers 35, 36, the element AND 37, the elements of UTI 38-40, the element NOT 41, the elements AND 42-44.

The device works as follows.

In the operating mode, the input of the device 20 receives a logical 1 signal. This signal sets the switch 10 to the information receiving mode from the second group of information inputs, multiplexers 6 to the information receiving mode from the information inputs 9 of the device, and to the input 23 of the control unit 21 , resets the trigger 35. The signal level at input 22 does not matter. Address signals entering inputs 18 pass through switch 10 and arrive at address inputs 3 of block 1 and select a word. The value of the information recorded in the selected memory location is

At the information outputs 5 of block 1, the information to be recorded in the selected memory cell enters the information inputs 9 of the device and through the multiplexers 6 enters the information inputs 2 of block 1, then the second information input of the switch 10 receives the write enable pulse from the input 19 of the device, which passes through the switch 10 and is fed to the input Write-read 4 of block 1. Under the action of a write enable pulse, the selected memory cell of block 1 records information, there is on information inputs 2 of block 1. The operation of the counter 11 and the control block 21 in an operating mode does not affect the operation of the device.

In the control mode, the input signal 20 of the device receives a logical O signal. This signal sets the switch 10 to receive information from the first group of information inputs, multiplexers 6 to receive information from the outputs of adders 7 and, to input 23 of block 21, cancels There is a flush reset mode 35 in which it was in operation. At the input 22 of the block 21, a 5Free logical 1 is supported. This signal resets the trigger 36, at the first input of the OR element 38, at the second input of the AND 37 element, at the input of the NO element 41, at the second input of the OR element 39, at the output 27 of the control unit 21 , at the input 13 of the counter 11, at the input of the element HE 34, at the first input of the element I 32, at the input of the control of the operating mode of the reversible counter 29 the level is maintained

The logical point 1. Reversible

counter 29 operates in the forward counting mode of pulses arriving at the synchronization input. At the second input of the element OR 40, at the first input of the element OR 39 a level is maintained

logical O. Reversible counter 29, having a k-1 bit, and trigger 30, operating in counting mode due to feedback from the inverse output to the information input,

in this case, they form a k-bit counter operating in the direct pulse counting mode, inputted to input 12. Thus, counter 11 operates in direct counting mode (operation Plus one). pulses input to input 12.

At the input 19 of the device begin to receive recording pulses. Polnos write pulses are negative. Since at the first moment of time after the control mode is set up, the trigger 35 remains set to the logical state O, then until the time point corresponding to the falling edge of the first recording pulse, the first inputs of the And 42, 44 elements will be maintained at the logical level 1. At the first input of the element And 43 will be maintained at a logic level of O. Therefore, the first write pulse to the input Write-read 4 of block 1 does not arrive and block 1 is in the shift mode. At outputs 5 of block 1, information appears corresponding to the address that identifies counter 11. A write pulse that goes through AND 44 and goes to the trigger inputs of trigger 8, writes this information to trigger 8. This same pulse the recording arrives at the input 12 of the counter 11 and switches it over. The address code from the outputs 14 goes through the switch 10 to the inputs 3 of the block 1 and selects Plus one cell.

In addition, the write pulse is fed to the input 24 of the control unit 21 and switches the trigger 35, which operates in the counting mode due to feedback from the inverse output to the information input. At the first inputs of elements And 42-44, logical levels appear, respectively, of logical O, logical 1 and logical O. Reading information into triggers 8 and switching the counter, performing operations Plus one, Minus two, is blocked. The information from the outputs of the flip-flops 8 is fed to the inputs of the ACmat 1mators 7, the other inputs of which receive the information corresponding to the selected cell in block 1. The information is equal to a modulo two of the previous and current selected cells in block 1 and comes from the outputs of the adders 7 through multiplexers 6 to informational inputs 2 blocks 1. Im-

the write pulse passes through the element, And 43, the switch 10 and is fed to the input Write-read 4 of block 1. The information present on the information inputs of the selected cell of block 1 is recorded. This same write pulse is fed to the input 24 of the control unit 21, axes; The switching of the trigger 35 operating in the counting mode is in the opposite state. At the first inputs of elements 42–44, logical levels appear, respectively, logical 1, logical 0 and logical 1. Next, the actions that were performed when the first write pulse was received (read) and then,

0 which were performed when the second write pulse was received (write), etc. The set of actions that

performed when two are received

write pulses (read and write),

5 is called a step. After a certain number of steps have been completed (after a certain even number of pulses has been written to the input 19 of the device), the first part of the control is completed, which is performed by maintaining the logical 1 level at the input 22 of the device.

Then, the second part of the control begins, in which the OS:

5 control. Logic 1 is supported at device input 22. The next write pulse is received at device input 19. At the same time, the actions that were performed upon receipt of the first write pulse were repeated (a send operation). After that, the input 22 of the device receives a logic level 1.

Since the information input is trig-

Gera 36 is left unconnected, it maintains a logical level of 1. However, before this trigger arrives at the sync input, the next write pulse is up to the point in time determined by its falling edge, the output of this trigger is maintained at the logical O level. elements 42-44 are installed, respectively, the levels of logical 1, logical O, and logical O. At the input 13 of the counter 11, the level of the logical O is set.

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at one time, the recording of information in block 1 as well as in triggers 8 is blocked. The next write pulse is supplied through the element 42 at the input 12 of the counter 11, as well as at the input 24 of the control unit 21.

When the input 13 of the counter 11 receives the level of logical About, then

in this case, switching of trigger 30 is blocked, switching of reversible counter 29 is always enabled when pulses are received at sync input 12. In addition, a logical level O is set at the control input of reversing counter 29, which corresponds to switching this counter to counting back (operation Minus one1) impulses arriving at its synchronous input. Since the outputs of this counter are connected only with the most significant k-1 bits of counter 11, the latter operates in the Minus two mode. When a write pulse arrives at the sync inputs of the flip-flops 35 and 36, these flip-flops are switched (the forward output of the flip-flop 35 sets the logic level O, the direct output of the flip-flop 36 is the logic level H). At the first inputs of the elements 42-44, the levels of logical 1, logical 0 and logical 1 are set. At input 13 of counter 11, a level of logical 1 is set, corresponding to the Plus operation one. This completes the second part of the control.

During the third part of the control at the input 22 devices supporting

The logic level is 1. The third part of the control ends after the device arrives at the input 19 of the same (even) number of write pulses, which was received in the first part. Subsequently, at the first input of the element 42, the level of logic 1 is constantly maintained. When the next write pulse arrives, information from the selected cell of block 1 is read into triggers 8. Writing information to block 1 is blocked. Counter 11. switches (Operation Plus One). At the input 24 of the control unit 21, the write pulse also arrives and switches the trigger 33, At the first inputs of the And elements 42-44, at the input 13 of the counter 11

the levels of logical 1, logical o and logical o are respectively tuned (recording information e block 1, operation Minus two). In this case, an entry is made in block 1 to the cell to which the last entry was made in the first part of the control. The recorded information in this case corresponds to a bitwise modulo sum of two information recorded in the currently selected cell and information recorded in the previous (relative to the positive direction of cell selection) cell. As a result, in the selected cell, information is restored that was in it until the last entry in the first part of the control. After performing the same number of steps (after the arrival of the same even number of write pulses) that was performed in the first part of the control, the state of all information cells of block 1 will correspond to the state of the same cells at the time control starts, if the control does not cause an error . After the control is completed, the logical input 1 is fed back to the device input 20. The fact of the presence or absence of an error can be determined by comparing the state of the cells of memory 1 before and after monitoring or by monitoring. code bits, if encoding of the recorded information is used.

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F o rumula from the recipe

A self-control storage device containing its memory, a counter, a switch, a control unit and multiplexers, the first information inputs of which are information inputs of the device, the outputs of multiplexers connected to the information inputs of the memory block whose outputs are information outputs of the device The control inputs of the multiplexers are combined and are the first input of the device operation mode setting, characterized in that, in order to increase the reliability of the control, the sum of tori modulo two and flip-flops, information inputs of flip-flops are connected to the corresponding information outputs of the memory block, synchronous inputs of the flip-flops are connected to the first output of the control unit, the second, third and fourth outputs of which are connected respectively to the first information input of the switch, the control and counting inputs of the counter, the outputs of the bits of which are connected to the information inputs of the first group of switch, the information inputs of the second group of switch are address inputs of the device, the first The control unit operation input of the control unit and the control input of the switch are connected to the first input of the device operation mode, the second input of the control unit operation mode is the same input of the device, the recording enable input of the control unit and the second information input of the switch are combined and

the enable entry of the device record, the second information inputs of the multiplexers are connected to the outputs of the corresponding modulo adders

two, the first inputs of which are connected to the corresponding information outputs of the memory block, the second inputs of modulo-two adders are connected to the outputs of the corresponding flip-flops, the switch output is connected to the Record-read input of the memory block, the switch group outputs are connected to the address inputs of the memory block.

Claims (1)

Claim A memory device with autonomous control, comprising a memory unit, a counter, a switch, a control unit and multiplexers, the first information inputs of which are the information inputs of the device, the outputs of the multiplexers are connected to the information inputs of the memory, the outputs of which are the information outputs of the device, the control inputs of the multiplexers are combined the first input of the job mode of the device, characterized in that, in order to increase the reliability of control, adders are introduced into it modulo two and triggers, the information inputs of the triggers are connected to the corresponding information outputs of the memory block, the sync inputs of the triggers are connected to the first output of the control unit. the second, third and fourth outputs of which are connected respectively to the first information input of the switch, controlling and counting inputs of the counter, the outputs of the bits which are connected to the information inputs of the first group of the switch, the information inputs of the second group of the switch are the address inputs of the device, the first input the operating mode of the control unit and the control input of the switch are connected to the first input of setting the operating mode of the device, the second input of the setting of the operating mode of the control unit is the device input of the same name, the write permission input of the control unit and the second information input of the switch are combined and are the device recording permission input, the second information inputs of the multiplexers are connected to the outputs of the respective adders modulo Ιθ two, the first inputs of which are connected to the corresponding information and outputs of the storage unit, the second inputs of modulo two adders are connected to outputs of the respective flip-flops, ^ 5 switch output is connected to the input Writing-reading of the memory block, the outputs of the switch group are connected to the address inputs of the memory block. Fie.Z