SU1288759A1 - Storage - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices, and can be applied in multiprocessor computing complexes. The aim of the invention is to increase the reliability of the device. It contains - blocks of 10 memory, buffer buffer fl1 (L o 00 00 cd with

Description

11, two groups of selectors 12, 13, two groups of correction blocks 14, 15, a single impulse generator 17, a correction block 16, a group of elements OR 18, a delay element 20, an OR element 21, and a local control block 19 containing AND 22 groups. , decoders 25, elements SHSh-NOT 23, a group of elements 24 delays and elements OR 26. Records1

The invention relates to computing, in particular to storage devices, and can be used in multiprocessor computing complexes.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of a memory device; in fig. 2 is a functional diagram of a decoder of a local control unit.

The device contains information 1, clock 2, installation 3 and control 4 and 5 inputs, control 6-8 and information 9 outputs of the device, memory blocks 10, buffer storage 11, first 12 and second 13 selector groups, first 14 and second 15 groups of correction units, correction unit 16, a single pulse shaper 17, a group of elements OR 18, a local control unit 19, a delay element 20 and an OR element 21.

The local control unit 19 contains (FIG. 1) AND 22 groups of elements, RSHI-NE 23 elements, a group of delay elements 24, decoders 25, and OR elements 26.

Each decoder 25 contains (FIG. 2) single pulse shapers 27, AND elements 28, delay elements 29, voltage level distributor 30, pulse shapers 31, SHIII-32 elements, comparison blocks 33 and triggers 34. Number of decoders 25, correction blocks 14 , selectors 12, elements OR 26, and elements AND 22 from each group of equal information is fed to the inputs of the buffer accumulator. Due to this, the device can operate in the modes of recording, storing and reading the same information in all the memory blocks or in the recording mode in one of the memory blocks of information that is different from that stored in all the other memory blocks. 2 Il.

but the number of memory blocks 10, the maximum value of which is determined by design considerations.

The number of elements OR 18, the elements OR-NOT 23 and the elements 24 delay, the number of groups of elements And 22, the correction blocks 15 together with the block 16, the selectors 13, the number of information 1, the clock 2 and the controller 4 and 5 inputs, The number of informational 9 and control 6 and 7 outputs is each equal to the number of information inputs of the buffer storage device 11, the maximum number of which is determined by the design capabilities of the elements from which the storage device 11 is made. The number of inputs 1 can be less, equal to or greater than the number of memory blocks 10 .

The device works as follows.

The device can operate in the recording mode of the same information in all the blocks 10 (Fig. 1) and in the mode in which information is recorded in one of the blocks 10 that differs from that recorded in the other blocks 10.

When the power is turned on, the device is installed in the original

condition for which the driver

17 (FIG. 1) generates a single reset pulse, on the leading edge of which, in the decoders 25, the distributors 30 (FIG. 2) are set to their initial position and, with some delay, the drivers 31 are started, each of which begins to form a sequence of pr - i rectangular pulses . On the front

the front of the same reset pulse is reset to drive 11, and at all outputs 6, the levels of logical zero are set, and in codes 7, logical units.

The reset pulse is output to output 8, as a result of which signals to inputs 1 and 2 of the device begin to be supplied. Each input 1 receives information in parallel binary code (self-correcting or non-self-correcting) in the form of information words, each of which contains the bytes of the cell address of block 10, the bytes of information, the bit of operation (if there is a unit in this bit, the information is recorded in block 10, and if there is zero in this bit, de - is read from block 10),

Each information word is written to accumulator 11 on the leading edge of a clock pulse that arrived simultaneously at the same input 2. At the same time at the same output 6, the level of a logical unit appears, prohibiting recording of the next information word at this input 1. A record of each information word at input 1 is made independently of the record at the other inputs 1.

Consider the operation of the device in the recording of the same information. on all entrances 1.

After recording the last information word, a series of identical words is sent to each block 14 from the outputs of the accumulator 11, in each of the blocks 14, errors are corrected (if they exist) by comparing all the recorded information words of one series with each other and also by determining the check bits and comparing them with the corresponding check bits (if they exist) in the recorded information words (if the information is represented by a non-self-correcting code) or by correcting and (if the information is It puts self-correcting code). The corrected information word from the output of each block 14 through the same selector 12 (at the control inputs of which there are logical zero levels) is fed to the inputs of the block of the same name 10. At the same time, the clock input of O

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As 10 comes from the output of accumulator 11 through a selector 12, a clock pulse, on the leading edge of which (if there is a unit in the operation of the information word), 10 bytes of information are written into the block, the code of the alarm is contained in the address part of this information word (if If the operation bit is zero, the information from block 10 is read to the same address. Thus, the same information at the same addresses is simultaneously written (or read) in all the blocks 10.

From the outputs of each block 10, the information word enters the same inputs of block 16 and blocks 15. From the outputs of block 16 and blocks 15, the corrected word through the selector 13 of the same name (on all control inputs of the selectors 13 is present to the logic zero code) goes to exit 9. On all exits 9 in this case appear the same informational words.

The operation of block 16 and blocks 15 is similar to the functioning of block 14.

After the appearance of a pulse at the clock output of the accumulator 11, the logical zero levels appear at the outputs 6, allowing writing to the accumulators 11 of the following series of information words. If systematic or random errors occur in any of the inputs 1 in the same information word of different series, or if this information word in different series systematically, accidentally lags beyond the predetermined allowable value in drive 11, then input 1 through the allowed total number of failures and delays is stopped, and the level of the logical unit from the same output 6 is not removed, prohibiting the transmission of information to the device on this input 1.

In the case of a one-time delay in the arrival of the information word at input 1 above the permissible value, the storage device 11 stops waiting for this word and rewrites the remaining information words one0 into its outputs

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the same series (herewith, one adds to the total number of failures and delays in this input 1 in the accumulator counter 11). The absence in this case at any input of any block 14 of the information word does not affect the correctness of the word received at the output of this block 14. The accumulator 11 is reset to its initial state by the signal at input 3.

In another mode of operation, one of the blocks 10 is used to store recording or reading information that is different from the information stored in parallel in all the other blocks 10. For this purpose, input 4, the same name as input 1 used for this purpose, is simultaneously sent to all decoders 25 receives the code of block number 10. Then a signal of logical unit is set to the same input 5, the leading edge of which in each decoder 25 decrypts the code of the block number 10. At the outputs of the decoder 25, in which the code at input 4 coincides with the record Previously, in the decoder 25, by the code of the block number 10, a binary code is generated that arrives at the selector 12 with the decoder 25 of the same name, which connects the block of the same name 10 to the corresponding input 1 and input 2, mine drive 11.

From the outputs of this decoder 25 through the element OR 26 of the same name with logic level 26 is also passed to the inputs of elements of the same name AND 22 of each group, the input of each of which receives the level of logical unit from the output of the corresponding decoder 25. As a result, one of the elements AND 22 opens in the group of the same name with the input 1, which will receive information in this selected block 10. From the outputs of the elements And 22 parallel binary code goes to the control inputs of the same selector 13, which Connects the output of block 10, the corresponding block 15 to the output 9. Thus, using any decoder 25, block 10 with the same name can be connected to any input 1 and output 9 with the same name.

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From the output of the decoder 25, the level of the logical unit through the element of the same name OR NOT 23 arrives at output 6, prohibiting the transmission of information along the selected input 1 to be shared with other inputs. At the same time, from the inverse output of this element OR-NOT 23, through element 24 of exit delay 7, a logical zero level arrives, which allows independent transfer of information to the corresponding block 10 regardless of the recording of a series of identical information words on other inputs 1. At the same time reading a series of identical information words on other inputs 1 does not stop.

The switching of any block 10 to independent operation is performed in the interval between receptions of a series of information words. The absence of an information word in this case on any input of any block 14-16 is corrected by the same block 14-16 with the help of information on its other inputs. Since the input 1 selected for the single operation begins to receive information that is different from the information on the other inputs 1 and does not coincide with it at the time of reception, the drive 11 is disconnected from receiving information on input 1 selected for the single operation, restoring of words.

After the end of the independent work on the selected input 1, the level of the logical unit from the same input 5 is removed, as a result of which the logical zero appears on the output of the selected decoder 25, which is applied to the OR 18, and the output delay 7 Logic unit level arrives. During the delay time of the element 24, the self-operating unit 10 is again connected to the like blocks 14-16.

On the leading edge of the logical unit signal from output 7, information on all inputs 1 is stopped, and storage device 11 is reset to input position through input 3. At the same time, at the output of the same name 6 a level of logical zero appears, indicating that the input 1, through which the information was recorded independently, is ready for collaboration with other inputs 1.

Claims (1)

Invention Formula A storage device containing a correction unit and memory blocks, the output of each of which is connected to the corresponding input of the correction unit, characterized in that, in order to ensure the reliability of the device, a buffer storage, selector groups, correction unit groups, a single impulse generator, an OR element, a group of OR elements, a delay element and a local control unit, one of the inputs and outputs of which are control inputs and one of the control outputs of the device, the other input of the local block the control and the first input of the OR element are connected to the output of a single pulse shaper, the output of the IL element is connected to the input of the delay element whose output is connected to the input of the buffer storage unit, the control outputs of which are connected to the first inputs of the OR elements, the clock output of the buffer memory is connected to the clock all entrances five 0 five 0 The first group of lecturers, the information outputs of the buffer accumulator are connected to the corresponding inputs of correction blocks of the first group, the outputs of which are connected to one of the information inputs of the selectors of the first group, the outputs of which are connected respectively to the inputs of memory blocks whose outputs are connected to the corresponding inputs of correction blocks of the second group and one of the information inputs of the selectors of the second group, the other information inputs of which are connected respectively to the outputs of the correction blocks of the second group and a correction unit, the other outputs of the local control unit are connected respectively to the control inputs of the group selectors and to the second inputs of the OR elements, the outputs of which and the output of the delay element are the other control outputs of the device, the installation input of which is the second input of the element. OR, the information inputs of the buffer accumulator and other information inputs of the selectors of the first group are information inputs of the device, the clock inputs of the buffer accumulator and other clock inputs of the selectors of the first group are the clock inputs of the device whose information outputs are the outputs of the selectors of the second group. Editor V. Petrash Compiled by T. Zaitseva Tehred V. Kadar Proofreader A. Obruchar Order 7813/50 l, um.m, Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, 7A Proektna St. 2