SU1149317A1 - Redundant storage - Google Patents

Abstract

A RESERVED STORAGE DEVICE containing the main and first backup data storage devices, the first parity signal generator and the control unit, characterized in that, in order to increase the reliability of the device, the information recovery unit, control information accumulators, code converter, local control unit, the second parity signal generator, switches, odd signal generator, second backup data collector, OR elements, AND element, NOT element, and BANNER element than one of the inputs and outputs of the first switch are the inputs and outputs of the device, and the other inputs and outputs are connected respectively to one of the outputs and inputs of the control unit and one of the outputs and inputs of the local control unit, the other inputs and outputs, which are connected to the outputs and the inputs of the main and backup data storages, the other inputs and outputs of the control unit are connected to one of the outputs and inputs of the information recovery unit, the other output and input of which are connected respectively to the first input of the second ommutatora and to the output of the third switch. the control outputs of the information recovery unit are connected respectively to the inputs of the first group and to the control input of the third switch, to the address and control inputs of the control information storage devices, to the control inputs of the code converter and to the control inputs of the second switch, whose outputs are connected to information the inputs of control data storage devices, one of the outputs of which are connected to the inputs of the second group of the third switch, one of the inputs of the first shaper of the signals and one of the inputs of the code converter, the other outputs of the control information storage devices are connected respectively to the first input of the third switch i and another input of the first signal generator (parity signal, to the second input of the third switch, to the third input of the third switch, the first input of the And and the first input of the BANNER element, the second input of which is connected to the output of the first generator of the parity signals and the input of the element NOT, the output of which is connected to the second input of the element AND whose output is connected with the first input of the first: about from the OR element, the second input of which is connected to the output of the BANNER element, and the output to the second input of the second switch and another input of the code converter, one of the outputs of which is connected to the inputs of the second generator of parity signals, the output of which is connected to the first input of the second OR element, the output of which is connected to the third input of the second switch, and the second input to the output of the odd signal generator, whose inputs and group of inputs of the second switch are connected to another output am code converter.

Description

The invention relates to computing, in particular, to storage devices with sequential sampling of information (tape drives, magnetic disks, magnetic drums, cylindrical magnetic domains (CMD), and charge-coupled devices).

A redundant storage device is known which contains main and backup drives and a control unit 1.

The disadvantages of this device are the large-scale hardware redundancy (100%) and the impossibility of protecting information in the event of a failure of the second (backup) drive.

The closest to the technical essence of the invention is a redundant memory device containing the main and one backup drives, the parity generator, the control unit, the modulo two, the inputs of the parity generator are connected to the input of the backup drive, the inputs of the modulo two are connected to the outputs of the main and backup storage, and its output is the output of the device, the inputs of which are the inputs of the main storage 2.

A disadvantage of the known device is low reliability, since it does not provide information protection in case of failure of two drives simultaneously.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the information recovery unit, data control accumulators, code converter, local control unit, second parity signal generator, switches, are entered into the backup memory device containing the main and first data backup drives, the first parity signal generator and the control unit. the oddness signal generator, the second backup data collector, the elements OR, the element AND, the element NOT and the element BAN, with one of the inputs and outputs switch are the inputs and outputs of the device, and the other inputs and outputs are connected respectively to one of the outputs and inputs of the control unit and to one of the outputs and inputs of the local control unit, the other inputs and outputs of which are connected to the outputs and inputs of the main and backup data storage devices , other inputs and outputs of the control unit are connected to one of the outputs and inputs of the information recovery unit, the other output and input of which are connected respectively to the first input of the second switch and to the output of the third comm the control outputs of the information recovery unit are connected respectively to the inputs of the first group and to the control inputs of the third switch, to the address and control inputs of control data accumulators, to the control inputs of the code converter and to the control inputs of the second switch whose outputs are connected to the information inputs of control information storage devices, one of the outputs of which are connected to the inputs of the second group of the third switch, one of the inputs of the first signal generator h and one of the inputs of the code converter, the other outputs of the control information storage devices are connected respectively to the first input of the third switch and another input of the first parity signal generator, to the second input of the third switch, to the third input of the third switch, the first input of the AND element and the first input of the BAN, the second input of which is connected to the output of the first shaper parity signals and the input of the element NOT, the output of which is connected to the second input of the element I, the output of which is connected to n The first input of the first OR element, the second input of which is connected to the output of the BANNER element, and the output to the second input of the second switch and another input of the code converter, are

d from the outputs of which are connected to the inputs of the second parity signal generator, the output of which is connected to the first input of the second OR element, the output of which is connected to the third input of the second switch, and the second input - to the output of the oddity signal generator, the inputs of which and the group of inputs of the second switch are connected to other outputs converter codes.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 and 3 are functional diagrams of the most preferred embodiments of the control unit and the information recovery unit, respectively.

The proposed device contains

 (Fig. 1) main 1 and reserve 2 data storage units, local control unit 3, first switch 4, control unit 5, information recovery unit 6, control information accumulators 7i-7z,

0 second 8 and third 9 switches, 10 codes converter, first 11 and second 12 parity signal drivers, odd parity generator 13, first element OR 14, BAN 15 element, NOT 16 element, AND 17 element and second OR 18 device. inputs and outputs 19, one of the inputs and outputs 20, another input 21, one of the control outputs 22-31 and another output 32 of block 6

information recovery, information inputs 33-36 and outputs 37-40 of control information storage 7i -7z, second 41 and third 42 inputs and input group 43 of second switch 8, other control outputs 44-47 of information recovery unit 6, first 48 and second 49 groups of inputs, inputs 50-52, first to third, and control input 53 of the third switch 9 (Fig. 1).

Control unit 5 contains (FIG. 2) control signal generator 54, clock pulse generator 55, micro-instruction accumulator 56, registers 57-61, decoders 62 and 63, encoder 64, AND-65 element group, and AND 66 element group. The data recovery section 6 contains (FIG. 3) a control signal generator 67, a clock pulse driver 68, a micro-command accumulator 69, a decoder 70, registers 71-74, a counter 75, and control signal drivers 76-86.

As a local control unit 3, an EC 5551M type storage control unit is used commercially produced by the domestic industry (when used as accumulators 1 and 2, for example, accumulators on a MD of type EU 5050 or EC 5056M), or other types of commercially available control units MI of the EU system.

Shaper 54 can be performed on IC K589IK01, drives 54 and 69 can be executed on IC K556PT7, registers 57-61 - on IC K 589IR12, drivers 78-86 can be implemented on two elements K155AG1, between which it is necessary to include a differentiating chain on the capacitor and resistor.

It is assumed that the information is written and read by fixed data arrays. The following arrays can be selected: for magnetic disk drives (NMD) - fixed data field of one disk sector, for magnetic tape drives (NML) - zone data field, for drives on cylindrical magnetic domains (CMD) - data page or data block (data page, multiplied by the number of parallel chips). Such a fixed array is defined as the minimum addressable unit of information (MAE).

Drive 7z has an information capacity of K NX 1 bit, where N is the MAE bit and K is the number of reads from MAE drives 1, is selected based on the minimum time required for reconstructing and rewriting information.

The proposed device works as follows.

As long as there are no failed drives 1 in the system, information is exchanged (data, address, control) via the outputs and inputs 19 between block 3 and the external device. At the same time, part of the information, reflecting the state of the drives 1, goes to the decoder 62 (Fig. 2). Thus, fault and failure information is continuously analyzed. Shaper 54 together with accumulator 56 operate on a short cycle, the main task of which is to timely receive information on errors and failures (this is possible because the speed of shaper 54 is several times higher than the speed of information exchange through inputs - outputs 19). If a failure occurs, and this failure is recoverable, the communication is interrupted via inputs 19, the device is transferred to the channel to enter recovery mode (via AND-OR 65 elements and register 57), block 3 is connected to block 6. The last link with block 3 is carried out through block 5: the output information enters AND 66 elements and then through register 61 is transferred to block 6. Input information for block 3 from block 6 enters register 58, and then through the AND-OR element 65 and register 57 is transmitted to switch 4. Part of the input control signal in the block 6 is supplied from the accumulator 56 through the register 60. After the information is retrieved, block 6 is connected through a switch unit 5 and 4 to the output 19 (FIG. 1).

The control signals for switch 4 come from accumulator 56, from where they go to register 59, controlled by decipher 63. It controls the reception of information in registers 60 and 61. For each recoverable failure, the encoder 64 generates the address of the initial command of the corresponding subroutine.

Since, depending on the contents of the accumulators 1 and 2, different recovery of information is possible, for each failure option there is a subroutine in its drive 69. The registers of block 6 are intended: 71 for sequentially receiving and issuing information, which the switches 8, 9 and block 5 exchange; 72-73 are used to issue addresses to the switches 9 and 8. The code is received in them by a signal from the decoder 70. The register 73 is designed to provide reception of information for the drives 7 and 7d. Register 74 sets and stores the mode of the SN / MF. Counter 75 sets the starting and ending addresses, as well as intermediate addresses for drives 7 7z.

Next, we consider the operation of the device as an example, when five drives 1 and two spare drives 2 are used (Fig. 1), while the drives representing information representing the sum modulo two data of the same bits of drives 1. Block 5 determines the moment termination of the recording in drives 1 and performs sequential access to them.

After, for example, two MAE of the same name of all the drives 1 are read, a bitwise calculation operation of the same MAE for writing to the drives 2 can be started. For this, read out of the drive 7, the five-bit word of the output 37 enters the driver 11 where the discharge of the first accumulator 2 is formed, which is through the element 3A. PRET 15, the OR 14 element and the switch 8 arrive in the same operation cycle of the accumulator 7i for writing to the accumulator 7 via the input 35. The switch 8 is controlled by the block 6, from which addresses 25, 31 and 44 are transmitted addresses, control pulses Signals "Record and" Overwrite. Similarly, the remaining bits of the MAE of the two sectors of accumulator 2 are formed, and, for example, after 2304 clocks of the accumulator 7, the transfer of the MAE from the accumulator 7 to the first accumulator 2 can be started. This procedure is performed by serially transmitting information on output 38 through the switch 9 at the input 21 to the block 6, from where the data on the inputs and the outputs 20 are transmitted to the block organizing their recording on the drives 2.

If one of the drives 1 fails, its bit information is restored. In addition, recoding information of accumulators 1 and 2 is performed so that the failure of any next of accumulators 1 is recoverable. At this moment, the formation of information of the second of the drives 2 is performed.

For this, information is read from accumulator 1 and the first of accumulators 2, which through switch 8 is written to accumulators 7 and 7j, of which five bits are read to driver 11, corresponding to accumulator 1, at outputs 37 and one bit, corresponding to drive 2, output 38. The result from the driver 11 through the prohibition element 15, the element OR 14 and the switch 8 enters the record in drive 7d at input 34 ("O - if there was no recoding;" 1 - if there was a recoding) and into the drive 7 at input 33 (recovered bit). In the same tact of the drive 7 | information from it goes to converter 10, where the recovered bit of the failing accumulator 1 comes from element OR 14. Depending on the value of the restored bit, converter 10 outputs to the driver 12 the received five-word received without change or the same inverted word to the driver 13, which form the result of evenness (oddness), written in the next cycle through the element OR 18 and the switch 8 to drive 7a. The presence of the former 13 (oddness) is caused by the following reasons: if any of the drives 1 fail, the corresponding bits in the drive TI are equal to “O, while the recovered bit of the failing drive 1 can be either“ O or “1. If he is "1,

5 then all five bits of the word are inverted, and therefore, "O, corresponding to the failing drive 1, becomes" 1. Thus, while the entire word was inverted, the discharge of the failing accumulator took its real

 value so that this error does not affect the formation of the parity bit, shaper 13 (oddness) is used. If, after recoding, any second drive 1 has failed, then its information

can be restored as follows: two MAEs are read into drives 7i and 72. Next, five bits are fed to driver 11, corresponding to drive 1 at outputs 37 and parity at output 38. Result

0 from the former 11 enters the BAN 15 and through the element NOT 16 on the element AND 17, which are controlled by the same bit of the second of the drives 2. If it is "O (no recoding of this word was performed), then for the recovered bit of the failing drive 1 the direct result from the output of the driver 11 is received. If it is "1, then the BAN 15 element does not pass the direct result from the driver 11, and the inverse result from the element NOT 16 passes through the element 17 and further to write to drive 7, and represents a restored bit

Until the second accumulator 1 fails, the second accumulator 2 can be used as a duplicate of the first accumulator 2, and in this case it is necessary to record a copy on it when recording information and generating the values of the first accumulator 2. This will not

0 to reconfigure information in the device in cases where the first drive 2 fails first (it is obvious that the likelihood of such a failure exists, although it decreases with the increase in the number of drives 1).

5 Thus, in the proposed system, almost continuous operation is ensured, since (assuming that two drives 1 do not fail at the same time and there is time for reconfiguration) after the failure of one drive 1, the device after some time required to overwrite information without losing it, again can function normally. In this case, the device can again be protected from the failure of one of the drives 1 and 2. Therefore, before the failure of the second of the drives 1, you can either add an additional drive 1 from the serviceable, but in cold reserve, or have time

repair the failed drive 1. It is very promising to use such devices in cases where it is necessary to periodically perform maintenance work, since disabling one drive for maintenance work does not affect the operation of the entire device.

The technical and economic advantage of the proposed device as compared with the known one is in higher reliability.

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Claims (1)

A RESERVED MEMORY DEVICE containing the main and first backup data stores, the first parity signal generator and the control unit, characterized in that, in order to increase the reliability of the device, an information recovery unit, control information stores, code converter, local control unit, are introduced into it parity signal generator, switches, odd signal generator, second backup data storage device, OR elements, AND element, NOT element and FORBID element n from the inputs and outputs of the first switch are the inputs and outputs of the device, and the other inputs and outputs are connected respectively to one of the outputs and inputs of the control unit and to one of the outputs and inputs of the local control unit, other inputs and outputs, which are connected to the outputs and inputs primary and backup data drives, other inputs and outputs of the control unit are connected to one of the outputs and inputs of the information recovery unit, the other output and input of which are connected respectively to the first input of the second switch and the output of the third switch, the control outputs of the information recovery unit are connected respectively with the inputs of the first group and with the control input of the third switch, with the address and control inputs of the control information storage devices, with the control inputs of the code converter and with the control inputs of the second switch, the outputs of which are connected to information inputs control information drives, one of the outputs of which are connected to the inputs of the second group of the third switch, one of the inputs of the first form the driver of the parity signals and one of the inputs of the code converter, the other outputs of the control information drives are connected respectively to the q first input of the third switch and another input of the first driver of the parity signals, to the second input of the third switch, to the third input of the third switch, the first input of the And element, and to the first the input of the element is BANNED, the second input of which is connected to the output of the first driver of the parity signals and the input of the element NOT, the output of which is connected to the second input of the element AND, the output to is connected to the first input of the first OR element, the second input of which is connected to the output of the FORBID element, and the output to the second input of the second switch and another input of the code converter, one of whose outputs is connected to the inputs of the second parity signal generator, the output of which is connected to the first the input of the second OR element, the output of which is connected to the third input of the second switch, and the second input to the output of the odd signal driver, whose inputs and the group of inputs of the second switch are connected to other code converter outputs.