SU1251188A1 - Storage with self-checking - Google Patents

Abstract

The invention relates to the field of computing and can be used in the construction of highly reliable storage devices. The aim of the invention is to simplify the known self-monitoring storage device. The device contains accumulators, bit comparison units, inversion blocks, a control block, a block of failures, an And element, a threshold element. Each block of one day comparison contains a reference element, a multiplexer. Each inversion block contains an OR element, an element of equal value, a control block. The control unit contains the group of elements OR, the group of elements AND, the group of elements NOT, the Threshold element contains the group of elements OR, the element AND, the delay unit. 1 il. (O ate C

Description

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The invention relates to computing, namely, storage devices.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of the proposed device.

The device contains accumulators 1 and 2, blocks 3 of a comparison, each of which consists of a comparison element 4 and a multiplexer 5, inversion blocks 6, each of which is executed as an OR 7 element and an unequality element 8, the first control unit 9 (convolution scheme modulo two), control block 10, containing a group of elements OR 1I, a group of elements AND 12 and a group of elements NOT 13, block 14 for fixing failures, containing first and second elements OR-NOT 15 and 16 and element And 17, a threshold element 18, containing a group of elements OR 19 and an element AND 2 0, delay unit 21, numeric outputs 22, numeric inputs 23, write-read control input 24, address inputs 25, control response output 26, access control input 27, second control unit 28 (reconciliation circuit two).

The device works as follows.

For address, numeric, operation and access indications, inputs 23, 24, 25, 27, respectively, the external devices specify the address codes, numbers, the access signal and the Write-read attribute.

It is assumed that during the operation Record the state of the numerical outputs

22 corresponds to the signals O, and in the operation Reading the signals O are set on the numeric input pnas

23- the number of numerical outputs for each of the drives 1 and 2 is more than two.

In the Record s mode, the accumulator 1, whose numerical inputs are connected directly to the numerical inputs 23, records the direct code of the incoming information to the inputs 23. The number code recorded in accumulator 2, whose numerical inputs are connected to pgana 25 through inversion block 6, depends on the value of the modulo two sum (parity) information of the numeric tires 23. When the number of units is even in the code of the bus number 23 to the numerical inputs

8I

The accumulator 2 from block 6 is supplied with the right code of a number, with oddness - the reverse code.

Modulo two sum (parity sign) is output by control unit 9 (modulo two convolution scheme), the output of which is used by control unit 10 to generate an inversion signal at the control inputs of the unequalities 8, the information of which is received from the bus number 23 through the elements OR 7. In the mode Read codes of numbers,

reads from drives 1 and 2 are compared to the bit by comparison elements 4 of blocks 3, and the comparison results are analyzed by failure fixing unit 14, threshold element 18 and second control unit 28 connected by inputs to the outputs of comparison elements 4,

With proper reading of information from drives 1 and 2, all elements 4 simultaneously form signals 1 or O, which ensures the formation of signal 1 at the output of the element OR-NOT 15 or element 17 and, therefore, the signal O at the output

element OR NOT 16 block 14 commit failure, which is a sign of correct information to be shared with the shanit.

In this case, the control unit 10 provides the formation of a signal on

the control inputs of multiplexers 5, blocks 3, transmitting information from the outputs of accumulator 1 to the output numeric tires 22 of the device, and block 21 — generating a device response signal on the response bus 26 corresponding to reliable information on the output numeric tires 22.

In case of malfunctions of the device, leading to errors in the information from drives 1 and 2, the signals O and I are generated at the outputs of the comparison elements 4, and the output of block 14 (the output of the element OR 16) - a signal 1,

corresponding to the device malfunction.

The output signals of the comparison elements 4 are analyzed by the threshold element 18 and the modulo two matching circuits of the second control unit 28 as follows.

one

The output signal of the threshold element 18 takes the value 1 when the number of signals 1 at its inputs is more than half the number of inputs, and O in other cases. Such a function of the threshold element I8 allows one to determine the parity of the information recorded in drives 1 and 2 and the encoding of information (forward or reverse code) recorded in drive 2, provided that at least one drive is healthy and the number of errors in reading numbers not The right drive is less than half the number of bits in a number. If the number of errors in this case is odd, it is possible to diagnose them by analyzing the parity of the numerical information of the accumulator 2 by the block 9 of the control. In case of an even number of errors, the diagnosis is rejected. The parity of the number of errors is determined by the control unit 28 associated with the inputs to the outputs of the comparison elements 4. The parity of information calculated from accumulator 2 is determined modulo two of the first block 9 control by modulo two. The discrepancy between the parity signs, determined by blocks 18 and 9, corresponds to an error in the information of accumulator 2, and a coincidence corresponds to an error in the information of accumulator 1.

The error correction procedure consists in switching information from the outputs of the operative accumulator to the output numerical buses 22 using multiplexers 5.

The analysis of the possibility of error correction and the correction procedure is carried out by the control unit 10, built, for example, on the basis of a programmable logic array containing groups of inverters 13, a group of elements AND 12, an element of OR 11, whose outputs are associated with control inputs of multiplexers 5, the inequality elements 8 and the delay unit 21.

The control unit 10 performs the decryption of the device states by analyzing the output signals of the blocks 14, .18, 9 and the read / write characteristic buses and commits to the output numeric tires 22 of the drive output information with correct information through the multiplexers 5.

In this case, the transfer of information from the outputs of drive 2 is accompanied by

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it is inverted by block 6 at the signal O from the input of block 18, since information with an odd number of units is recorded and read from accumulator 2 in the reverse code.

If there is a correctable error, delay block 21 provides for a delay on the signal on response bus 26 to the correction time of information on signals from blocks 14 and 10. In case of failure to decode the error, the response signal on bus 26 is not generated.

The threshold element I8 can be built on two-input elements OR 19, the inputs of which are associated with the corresponding outputs of the comparison element 4, and the outputs with the inputs of the AND element 20 (the number of bits of the number is assumed to be even). In this case, its operation corresponds to the case considered for a single error in the information read from drives 1 and 2.

Claims (1)

Invention Formula A self-monitoring memory device containing the first and second drives, the address and control inputs of which are combined and the corresponding inputs of the device, the numerical inputs of the first storage device are the corresponding inputs of the device, the outputs of the first and second drives are connected respectively to the first and second inputs of blocks of the same size comparison, the first outputs of which are connected to the inputs of the block for fixing failures, the output of which is connected to the first input of the delay unit, the second input of which is connected to the pack equalizing the input of the first accumulator, the output of the delay block is the control output of the device, the second outputs of the bit comparison blocks are the numerical outputs of the device, the first and second control blocks, which in order to increase the data capacity of the device, it contains inversion units, a control unit and a threshold element, the inputs of which are connected to the first outputs of the one-time comparison units and to the inputs of the first control unit, the output of which is connected to the first input of the output unit, output The threshold element is connected to the second input of the control unit, the third input of which is connected to the output of the failure-fixing unit, the fourth input of the control unit is connected to the output of the second control unit, whose inputs are connected to the first outputs of the inverting units, the second outputs of the inverting units are connected to the numerical inputs of the second accumulator and to the third inputs of the bitwise comparison units, the first inputs of the inverted units The second inputs of the inverting units are connected to the outputs of the second storage unit, the third inputs of the inverting units are connected to the first output of the control unit, the second output of which is connected to the fourth inputs of the one block comparison unit, the third output of the control unit is connected to third block delay block. Editor A. Ogar Compiled by S. Shustenko Tehred I.Gaydosh Proofreader M.Demchik Order 4419/51 Circulation 543. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4