SU1501171A1 - Self-check storage - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to increase the reliability of the device due to the possibility of correcting the even errors of any multi-bit storage element of one of the drives and detecting certain types of multiple errors in the same bits of both drives. The device contains accumulators 1 and 2 consisting of multi-bit storage elements 3, comparison units 4, inversion units 7, control unit 10, delay unit 11, control unit 12, table decoding unit 13. The table decoding unit has been entered into the device to decrypt the results compare data read from the main and duplicate drives to determine and correct the errors of one of the multi-bit storage elements on the basis of which the drives of the device are based. 1 il.

Description

k-o /

-about

7

types of multiple errors in the same bits of both drives. The device contains accumulators 1 and 2 consisting of multi-bit storage elements 3, comparison units 4, inversion units 7, control unit 10, delay unit 11, control unit 12, table decoding unit 13. In the device is entered

15011714

The table decoding unit for decoding the results of one-by-one comparison of information read from the main and duplicate drives for determining and correcting the errors of one of the multi-bit storage elements on the basis of which the drives of the device are built. 1 il.

The invention relates to computing, namely, storage devices (memory)

The purpose of the invention is to increase the reliability of the device due to the possibility of correcting even errors within one multi-bit storage element of one of the drives and detecting certain types of multiple errors in the same bits of both drives.

The drawing shows a block diagram of the device.

The device contains drives 1 and 2 of information consisting of multi-bit elements 3, for example, a BIS memory with byte organization, blocks

4 comparisons consisting of elements

5 comparisons of the multiplexer 6, similar to the well-known inversion blocks 7, consisting of the element OR 8 and the element of inequality

9, a control unit 10 performed on a modulo-two adder, a delay unit 11, a control unit 1 / control, which is known to the known, a table decoding unit, made for example in the form of microcircuits. PZK KJ809P SHCHI1F1. input numbers J4, B1 input number J5, references J6, read-write 17, address J8, answer 19. The device works as follows ..

Address, input numeric, write-read-write 18,14,17,16, respectively, address codes, numbers, access signal, and write-read sign are set by external devices.

It is assumed that, during the operation Write, the state of the output word lines 15 corresponds to the signals O, and during the operation Read signal O is set to the input numerical values

0 5

0

five

0

with

0

14, the number of numeric bits n of drives 1 and 2 is even, the number of numeric bits m of multi-bit elements is the same for both drives.

In the Record in Drive 1 mode, the numeric inputs of which are connected by the input numeric boxes 14 directly, the forward code of the incoming information is recorded.

The number code recorded in the accumulator 2, the numerical inputs of which are connected to the input numerical bus 14 through the inverting blocks 7, depends on the value of the sum modulo two (parity) information of the input numerical values 14.

With an even number of ones in the code, the numbers on the bus are 14, i.e. if their modulo two sum is zero, the inverse code of the number is fed to the numeric inputs of the accumulator 2 from the inverting units 7, for odd ones the direct code is supplied. Modulo two sum (parity) is generated by control unit 10 (modulo two convolution scheme), the output of which is used by control unit 12 to generate an inversion signal at the control inputs of the inequality elements 9, the information inputs of which receive the code of the recorded number from the input buses numeric 15 through elements OR 8. At a read signal on read-write bus 17, codes of numbers read from multi-bit elements 3 of drives 1 and 2 are removed by bits 5 of block 4 comparison. Block k ntrol JO form two code value sum modulo number schitshaemogo from the accumulator 2, n output signals of the elements 5 and the signal from the comparison unit analiziruet- exit table unit 13 dekodirova51

The inputs of which are connected with the outputs of the comparison elements 5, the control unit 10 and the control unit 12 associated with the output of the control unit 10 and the numerical outputs of the table decoding unit 13. The combination of the signals 00, 01, 10, 11 on the first and second outputs of block 13 corresponds to four states of the device:

-the device is working properly

- drive 1 is defective (error at the output of drive 1),

- drive 2 is faulty (error on output of drive 2),

-the device is inoperable. These four combinations of the output signals of block 13 in the case of the execution of this block on the basis of the ROM chip are written into the ROM by addresses, the codes of which form four corresponding sets A ,, A,

Ag, A, are defined as follows:

AO is a two-element set of (n + 1) -disk codes containing zero (one) in (n + O-bit, which is the output of the control unit 10 and one (zero) in the remaining n-bits, which are outputs of the elements of comparison 5j

B is a set of (n +) - bit codes containing a one or zero in (n + 1) bit, at least two units (zero) in the bits to which the outputs of the elements 5 correspond

comparisons related to the pen

only one input

their multi-bit elements 3 are accumulator 1 and zero (ones) in the remaining bits;

B is a set of (n + l) -disk codes containing a one or zero in (n + 1) bit, at least two units (zero) in bits that correspond to the outputs of comparison elements associated with the second inputs with only one from multi-bit accumulative elements 3 accumulator 2 and zeros (ones) in the remaining bits)

In (B) the set of codes containing the unit in (n + 1) bit, and

sixteen

also zeros and ones in the remaining n bits, with the number of ones (zeros) being odd and less than n / 2; Bt (B) is a set of (n + 1) -disk codes containing zero in (n + 1) bit, as well as zeros and ones, in the remaining n bits, and the number of zeros (ones) is odd and less than n / 2

Sets B, and B correspond to repeated errors in reading, including even, information from one of the multi-bit elements of 3 drives 1 and 2, respectively.

Sets B, B,

(V.V) soot

0

0

These are errors of odd multiplicity when reading the information of the first (second) accumulator 1.2 with an arbitrary distribution of errors according to its multi-digit elements, 3. Combine A Wu. B, V B5iA2 P2 U Bg form the sets A and A, corresponding to the errors when reading information from drives 1 and 2, which allow them to be decoded by the table decoding unit 13, both for odd and even errors.

The complete code set A (n + 1) of the bit codes at the address inputs of the table decoding unit 13 is the union A AV Aj. A is the code set corresponding to the configuration of non-decoding errors, i.e. when an information device is not working, if the information from drives 1 and 2 (n + 1) is correctly read, the bit codes at the inputs of table 13 are decoded into the set AJ, block 13 at their numerical outputs form the OOJ code. The control unit 12 generates at the inputs of the multiplexers 6 of the blocks 4 signals transmitting information from the outputs of the accumulator 1 to the output numeric tires 15 of the device, and the delay unit 11 forms the response signal of the device on the answer bus 9 corresponding to the correct information on the output numeric tires 15.

In case of malfunctions of the device, leading to errors read by information from drives 1 and 2, block 13 determines the code at its address inputs to one of the disjoint sets A, Aj, A, forming the corresponding signals in control block 12.

The control unit 12 performs the decoding of the device's devices by analyzing the output signals of the block 13. If there are errors correcting (codes o, 1 JO at the output of the block J3), the block J2 produces the signals at the control inputs of the multiplexers 6 and the inverting blocks 7, which ensures KOMMyTaujco on the output numeric tires 5 of information from the output of the accumulator with the correct information, which, if necessary, is inverted by the inverting blocks 7, since information with an even number of units is written and read from pitted 2 in reverse code. The delay unit 11 delays the response signal on the bus 19 for the duration of the information correction. If there is an error that does not allow correction (code 1 at the output of table decoding 13), the control unit 13 blocks the response signal to the response bus 18.

In connection with the possibility of analyzing the result of comparing the information of drives 1, 2 (coincidence or mismatch) and the parity value of the drive information generated by the control unit 10, the proposed device, unlike the known, allows detecting an even number of errors such as inverting all bit bits, for example, due to malfunction of control unit circuits. Errors of both drives in the same bits of a certain address are also detected if the number of errors in each drive is odd.

Claims (1)

Claims. A self-monitoring memory device containing the first and second drives, each of which consists of multi-bit memory elements and has an information width L km (where m is 2,3,4-width of the storage elements. 0 five 0 five 0 five 0 five ki, 2,3 ... - coefficient), address inputs and inputs for recording and accessing of storage elements are combined and are respectively address inputs and inputs for recording and enabling device access, control unit, control unit, delay unit, one-to-one comparison blocks , inversion units, the first inputs of which are connected to the information inputs of the storage elements of the first storage device and are information inputs of the device, the i-th information input and the L-th information output of the j-ro storage element of the first Acopitel are connected respectively to the first inputs of the nth inversion block and the nth block of one bit comparison (where i is 1,2, ..., m, j is J, 2, ..., k – ha, n. (j-1) m + i), the first outputs of the one-bit comparison blocks are information outputs of the device, the second inputs of the one-bit comparison blocks are connected to the first output of the control unit, the second and third outputs of which are connected respectively to the second inputs of the inverting blocks and the first the input of the delay unit, the second input of which is connected to the device enable access input, the output of the delay unit is the device ready output, the inputs of the monitoring unit are connected to the first outputs of the inverting units, the output of the monitoring unit is connected to the input of the parity signal of the control unit, whose recording input is the same input of the device, which is different from in order to increase the reliability of the device, a tabular decoding block is inserted into it, the inputs of which are connected to the second outputs of bitwise comparison blocks and to the output of the control unit, the outputs of the tabular decoding block are connected to input The error code of the control unit, the th information input and the 1st information output j-ro of the storage element of the second accumulator are respectively connected with the second output S-ro of the inverting unit and the fourth input of the B-GO comparison unit and with the third input of the S-ro inverting unit and with the third input of the S-ro comparison block (where j I ... m, j 1, ... km), l); j - (k-Dm + lrkm j - I -J- m j t--1 g2 w j 2t-ItZt j - I -J- m j t--1 g2 w j 2t-ItZt