SU439020A1 - Autonomous control storage device - Google Patents

Description

one

A standalone monitoring device with independent control is known, containing accumulative modules, an address register consisting of a module number register, the output of which is connected to the input of the module number decryptor and a cell number register, the output of which is connected to the inputs of the address module of accumulative modules, an output register connected with control unit.

However, the known device in case of failure of one or several cells of the storage module has to be repaired. In addition, the repair does not guarantee proper operation of the device in the event of a repeated failure of the same module. In some cases (for example, using integrated technology), such repair is generally impossible, and the correction of programs developed in the language of programming requires large overheads of working time.

The proposed storage device differs from the known one in that it comprises a module switching unit, one input of which is connected to the output of the decoder of the module number, and the output to the inputs of the storage module; the correction unit, whose outputs are connected respectively to another input of the switching unit of modules and the output register, and the inputs to the outputs of the OR circuit blocks entered into the device, inputs

which are connected to the outputs of word registers of accumulative modules. This makes it possible to increase the reliability of the circuit.

FIG. 1 shows a block diagram of the device; in fig. 2 and 3 - embodiments of the switching unit modules; in fig. 4 - one of the possible schemes of the correction unit.

Address Register 1 with information entry

2 consists of a register of module number 3 and a register of cell number 4. The output of register 3 is connected to the input of the decoder of the module number 5. The output of the decoder 5 is connected to input 6 of the switching unit of modules 7. Each

Out of 2p buses 8, the output of block 7 is connected to the control input of the corresponding storage module 9 (2n is the number of storage modules). The output of the register 4 is connected to the input of each of the address registers 10. The output of each of the registers of the word 11 of the cumulative modules 9 through the OR 12 circuit block and the OR 13 circuit block is connected respectively to the inputs 14 and 15 of the correction unit 16. The 17 block output 16 is connected with weekend

register 18 having output 19 and input 20. Register 18 is connected to input 21 of block 16. Outputs 22, 23 of block 16 are associated respectively with registers of word 11. Output 24 of block 16 is connected to input 25 of block 7. Registers 1 and 18, blocks 7 and 16 and the storage modules 9 are connected to the control unit 26, which has an input 27 and an output 28.

The switching unit of the modules 7 (Fig. 2) contains the status register of the modules 29, having l bits. The output of register 29 is connected to one of the inputs of the OR 30 and 31 OR circuit diagrams. The output buses of blocks 30 and 31 are connected to input 8 of block 7. The inputs 6 of block 7 are connected to the other inputs of blocks 30, 32, respectively. .

Register 29 and outputs of blocks 30 and 31 are associated with block 26.

Another variant of the switching unit of the modules 7 (Fig. 3) contains the state register of the modules 33 having 2p bits. The input of the register 33 is connected to the input 25 of the unit 7. One output of the register 33 is connected to the input of the switch 34, one output of which is connected to the block 26 and the other to one of the inputs of the OR 35 circuit. Another output is connected to the other input of the block 35 register 33. The output of block 35 is connected to the output 8 of block 7.

The register 33, as well as the output of block 35, are associated with block 26.

Correction block 16 (Fig. 4) consists of two registers of the words 36 and 37, the inputs of which are connected respectively to the inputs 14 and 15 of the block 16, and the outputs through the coding and decoding blocks 38 and 39 with the block of OR 40 circuits. The output 40 is connected to the output 17 of the block 16. The input 21 of the block 16 through the blocks 38 and 39 is connected to the outputs 22 and 23 of the block 16. The outputs 41 of the block 38 and 42 of the block 39 are connected to the control circuit 43, the outputs of which 44 and 45 are connected respectively to the inputs of the blocks 38 and 39 The output 46 of the circuit 43 is connected with the output 24 of the block 16 and the block 26, the output 47 of the circuit 43 - with the block 26.

The device works as follows.

The address of the cell to be addressed is written to register 1 at input 2 (see Fig. 1). A single signal that occurs on the output stitch of the decoder 5 selected according to the contents of register 3 enters block 7. Block 7 sets one of two possible modes of operation in the device depending on the presence or absence of failures in the cells of accumulative module 9.

Consider the first mode (no failures in the cells of the cumulative module).

Block 7, using a single signal from the decoder 5, connects the corresponding storage module 9. The contents of register 4 are accepted into the address register 10 of the connected module.

The information in register 11 of cumulative module 9 is recorded from register 18 through block 16 at its input 21 and output 22 or 23.

When reading, the contents of register 11 through block 12 or block 13 enters block 16. Block 16 determines the presence of failures in the cell of the connected storage module 9, and, if the cell is healthy, the information word enters register 18.

If a failure is detected in the cell of the cumulative module 9, the device is transferred to the second mode of operation, as follows. The signal "Failure from block 16 goes to block 7, where the malfunction of the / -th storage module 9 (, 2, ..., 2p) is recorded, and to block 26. By this signal information is transferred, for example, from 2n - / + 1 -H storage module, which should be duplicated for the / -th module in another storage device (not shown). In the vacated cells of the cumulative module, the information recorded in the cells of the same name in the failing module is entered.

Consider the second mode (the presence of failures in the cells of the cumulative module).

Block 7 connects the ith and 2n - / + 1st storage modules with a single signal from the decipheror 5. The contents of register 4 are taken to the corresponding address registers 10.

When writing, the information word comes from register 18 to block 16 and further to the corresponding registers. When reading, the contents of these registers arrive appropriately through blocks 12 and 13 in block 16. Block 16 corrects the read information, after which the information word from output 17

block 16 is written to register 18. If correction is not possible, from block 16 to block 26 a signal is received “unrecoverable error. In the case of using the device in the first embodiment of block 7 with the n-bit register of module status (see Fig. 2), accessing the old address to the cells of the duplicate accumulating module 9 is prohibited by software, since block 7 itself does not provide this prohibition. If a

If block 7 is used with the 2n-bit register of the module status (see Fig. 3), when accessing the cells of the backup accumulating module at the old address, block 7 prohibits its connection and issues a “Repeat. This means that the information stored in the 2n - / + 1 st storage module is transferred to another storage device.

Subject invention

A self-monitoring memory device containing accumulative modules, an address register consisting of a module number register, the output of which is connected to the module number decryptor input, and a cell number register, the output of which is connected to the inputs of the accumulative module address registers, output register, connected

with a control unit, characterized in that, in order to increase reliability, it contains a module switching unit, one input of which is connected to the output of the decoder number of the module, and the output to the inputs

cumulative modules, the correction unit, the outputs of which are connected respectively to another input of the switching module of the modules and the output register, and the inputs to the outputs

blocks of “OR” input into the device, the inputs of which are connected to the outputs of word registers of accumulative modules.

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