SU1215140A1 - Storage with self-check - Google Patents

Abstract

The invention relates to computing and can be used in the manufacture of LSI memory with a large crystal area, as well as in memory systems of increased reliability. The purpose of the invention is to simplify the device. The device contains a matrix drive with check bits for recording correctively. a code and a check bit indicating that the recording was made in a forward or reverse code, a coding unit, switches, a number register, a driver of control signals, a comparison unit. The device corrects twice the error (two failed bits). In this case, in the event of failure of the recorded symbols to fail, the word is written into the drive in the return code, and in the case of a single bit disagreement, a single error is made, which corrects with the redundant code, 3 sludge. (L

Description

one

The invention relates to computing and can be used in the manufacture of BIS chargers having a large area of crystals, as well as in memory systems of high reliability.

The aim of the invention is to simplify the device.

Fig, 1 shows the functional scheme of the proposed device; in fig. 2 and 3 are functional diagrams of the most preferred embodiments of the first and second switches, respectively.

The circuit includes (fig. 1) information input 1, address input 2 for determining the bit number, adrenal input 3 for determining the line number, control inputs 4-6 and information output 7, the device also contains a decoder 8 row addresses, matrix storage 9 with check bits 1.0 for writing the correction code and check bit 11, amplifiers 12-14 with inputs 15-17 coding block 18, first 19 and: second 20 switches, 21 register numbers, correction code register 22 with an additional discharge 23, groups of elements And 24-26 from the first to the third, Registers control code 27, the first 28 and second 29 OR elements, shaper 30. The control signals, srpvneni unit 31, decoder 32 column address, the first 33 and second 34 two adders modulo

The first switch 19 contains (FIG. 2) the elements AND 35 and the element OR 36, the Second switch 20 (FIG. 3 contains the elements AND 37, 38 and 39 and the elements NOT 40,

. The coding block 18, the pilot of the pilot signals 30 and the block 31 of the comparison can be performed on the basis of modulo two adders,

In the proposed device, a correction code with a minimum code distance of three is used, and the coding block 18 must be executed in accordance with the check matrix of the code used.

The device works as follows.

Consider the operation of the device in three cases: there are no failed bits; there is one failing bit;

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There are two failed bits in the cells of accumulator 9 (FIG. 1),.

The first case (there are no failed bits), the recording of information is carried out as follows. A recordable character is fed to input 1, and an address to inputs 2 and 3. First, at the address at input 3, a line is read from drive 9

0 through amplifiers 12–14 to registers: 21–23, in resolution 23 of which code O. At block 18, the direct code of the read word is received. Since there are no failed bits and, therefore, there are no errors, the code recorded in register 27 from block 18 and the code in register 22 are the same. Therefore, the code O is present at all outputs of the imaging unit 30. At the output of the element OR 29, also the code O, Element H 25 is closed and therefore, when the signal to input 6 is fed, the size of discharge 23 does not change. At the output of block 31, the code is O, meaning a mismatch, since the bit numbers in the line are numbered from first to K - and, where HJ is an integer, and zero signals come from the outputs of the imaging unit 30. When a signal is input

.JQ 5 element AND 26 is closed and therefore

also the contents of bit 23 does not change. The written character in the direct code goes through the corresponding element AND 39 of the switch 20 (FIG. 3) to the register 21, the direct code of the word is transmitted to the input of the block 18, and in the block 18 the check bits are formed. When a signal is applied to input 4, the contents of register 21, register 22, bit 23 is written to drive 9 through amplifiers 12-14.

When reading data, in the same way as when writing, the string is read into registers 21-23. Through one of the AND 35 elements and the OR element 36 of the switch 19 (FIG. 2), the corresponding word in the direct code is fed to the input of the adder 33 and then to output 7. Since there was no error, the contents of bit 23 when the signal to input 6 is applied does not change. When a signal is detected at input 4, a string is written to drive 9.

55 The second case (for example, there is one failed bit). We assume that the failed bit distorts the recorded character. Recording information is produced

35

40

45

50

3

in the following way. First, the row is read into registers 21-23. Through switch 20 from input 1, register 21 receives the forward or reverse code of the written character depending on the contents of bit 23. As there is an error, the codes at the outputs of registers 27 and 22 do not match. At the output of the imaging unit 30, a code appears indicating the number of the failed discharge. In this case, the output of the element OR 29 code and the signal applied to the input 6 of the element And 25 opens. Code 1 through the OR element 28 is fed to the inputs of all the bits of the registers 21 and bit 23, and the contents of these bits are inverted. Block 31 compares the bit number, which is distorted, and the bit number in the line in which the new information should be recorded. If these numbers do not match, then at the output of block 31 ko. O. When the input signal 5 is applied, the element And 26 is closed and the contents of the bits of the register 21 and bit 23 do not change, i.e. there remains a reverse code. This leads to the fact that when a signal is applied to input 4, the return code of the word is written, the corresponding check bits and code I in bit 23 are in drive 9. The result is that the recorded symbol and the nature of the discharge failure coincide and no word distortion occurs. If the bit numbers at the inputs of the block 31 are the same, the code 1 is generated at the output of block 31. At the output of the adder 34, a sum is formed on the module of two read bits and the value of the bit that will be written to this place. If they match, then

at the output of the adder 34 code O and the element And 26 is closed. Therefore, when

The signal to input 5 does not change the contents of bit 23, i.e. code 1 is saved there and, similarly, the word is written back to the accumulator 9. If the read and write bits do not match, output 34 of the code 1 is code 1. Therefore, when the signal at input 5 is input, the element 26 also opens the contents of the register 21 and bit 23. is inverted, i.e. there is now a direct code. In this case, when a signal is applied to input 4 to drive 9, the direct code is written sla115140 "

However, the error is also not introduced by the refusal.

When reading information, the word in the inverse code is written to registrar 21. By a signal from the decoder 32 through the switch 19 with inverting on the adder 33, the corresponding symbol is transmitted to output 7. If the failure occurred during

10 storing data, then when the direct code of the word is read with an error and with O in bit 19, the code 30 on the outputs of the former indicates the number of the failed digit. If a

15 the number of the failed bit and the number of the read bit at input 2 are the same, then the output of block 31 is code 1. This code is sent to the sum - torus 33 and inverts the distorted symbol. If the number of the failed bit and the number of the match number at the input 2 do not match, then the read character is output to output 7 unchanged. Similarly, the device pa-.

25 bots and in the presence of code I in bit de 23 of register 22,

The third case (there are two failed bits). In this case, three options are possible: the type of refusal of two bits is matched with the characters to be written; the nature of the failure of one bit is consistent with the written symbol, and the nature of the failure of another bit is not consistent with the record of the symbol; ha35

failure rate of two digits not

matched with writable characters.

In the first version, the device works in the same way as the first case.

40 (no failures). In the second version, the device works in the same way as the second case. The only difference is that after each reading of the line, the contents of register 45 are inverted. Therefore, one and the other failed bits are alternately matched with the recorded symbol. However, each time a single error occurs, which is corrected with the redundant code.

In the third variant, due to the inversion of the word, the refusal patterns are coordinated. 55 two digits with recorded fmls. Subsequently, when reading and writing data in the line of accumulator 9, the reverse code of the word is entered.

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Claims (1)

Invention Formula A self-contained memory storage device containing a matrix drive whose address inputs are connected to the outputs of the row address decoder, a group of amplifiers, a coding unit whose outputs are connected to the first inputs of the AND elements of the group and the inputs of the control code whose outputs are connected to one of the driver inputs control signals, the register of numbers, the register of the correction code, the first modulo-two adder, the decoder of the address of columns and the first element of the 1SH, one of the inputs and outputs of amplifiers The first group and one of the amplifiers of the second group are connected respectively to the digital and to one of the control outputs and inputs of the matrix accumulator, and the other inputs and outputs are connected respectively to one of the outputs and the number register input and to the inputs and inputs of the first group of the correction code register, the outputs of the second group of which are connected to other inputs of the pilot signal generator, one of the outputs of the number register is connected to the inputs of the coding block, the other inputs of the amplifiers of the second group are connected to the outputs of the ale Groups And the second inputs of which are the first control input of the device, it is necessary that, in order to simplify the device, the second modulo two adder, the switches, the comparison unit, the AND elements and the second OR element are entered into it, and the outputs of the first and the second element AND are connected to the inputs of the first element OR, the first input of primary 6 Element I is connected to the output of the second SHS element whose inputs are connected to the outputs of the pilot signal generator and one of the inputs of the comparison unit, the other inputs of which are connected to the inputs of the column address decoder, the outputs of which are connected to one of the inputs of the first and second switches, the output of the comparison unit connected to the first inputs of the first modulo two and the second element And, the second input of which is connected to the output of the second modulo adder two, the first input of which and the second input of the first modulo adder two are connected to the output of the first switch, the other inputs of which are connected to other outputs of the number register, the other inputs of which are connected to the outputs of the second switch, the other inputs of which are connected respectively to the second input of the second adder module two and with the third input of the first modulo-two adder and the first output of the register of the correction code, the first input of which is connected to the output of the first OR element, and the second the input and output are connected to one of the outputs and inputs of another amplifier of the second group, the other input and output of which are connected to the other control output and the input of the matrix the drive, the output of the first and the second input of the second modulo two adders are respectively the information output and the input of the device, the second and third control the inputs of which are, respectively, the second input of the first and third input of the second elements AND, IG Om21 OTG 1215140 OmZr From 32 i i J5 in e um / Ll 35