SU448480A1 - Memory device - Google Patents

Description

The invention relates to the field of storage devices (memory).

A memory is known that contains a drive connected to the address register, a register of the power of the correction code, one output of which is connected to the inputs of the coding and decoding units and one of the inputs of the first comparison circuit whose output is connected to the control unit, and the other input to the output of the determination circuit the multiplicity of failures and one of the inputs of the second comparison circuit, the other input of which is connected to the output of the decoding unit, the generation unit of correction words, the output of which is connected to one input of the distribution block, etc. The input is connected to the output of the AND circuit and one of the code word registers, and the output via the OR circuit to the decoding unit, the circuit for determining the failing bits, whose inputs are connected to the outputs of the code word registers, and the output to the information input “And and to the input of the failure multiplicity determination circuit.

However, the known memory has a low effective capacity.

The proposed memory is different from the fact that it contains an additional drive, the address output of which is connected to the outputs of the higher bits of the register

addresses, and the bit input and output, respectively, to another output and input of the force register of the correction code.

The drawing shows the block diagram of the proposed memory. It contains the address register 1 with input 2, consisting of the register number of the cell 3 and the register of the page number 4, which form the leading bits of the register 1. The output of register 1 is connected to input 5 of drive 6, and the output of register 4 is connected to address input 7 drive 8. The capacity of drive 6 is p pages, the capacity of drive 8 is p cells. The bit output 9 of the accumulator 8 is connected to one of the inputs of the force register of the correction code 10, one of the outputs of which is connected with the bit input of the accumulator 8.

The code output 11 of the drive 6 is connected to the code inputs of the registers 12, 13 of the code word. The code output of register 12 is connected to one input of the circuit OR 14, whose output through a valve 15 is connected to the output of the correction word generation block 16, and the output of the circuit block

"Or 14 is connected to the code input of the decoding unit 17. One control output of the block 17 is connected to the control unit 18 having an input 19 and an output 20. The information output of the block 17 is connected to one input

The OR circuit 21, with another input, is connected to the inverse information output of the register 13, and the OR circuit output of the circuit OR is connected to the information output 22 of the device.

The information input 23 of the device is connected to the information input of the coding block 24. The code output of the block 24 is connected to one input of the OR 25 block of circuits, the inverse code output of the register 12 is connected to another input, and the output of the OR 25 circuit block is connected to the bit drive input 6.

The code outputs of the registers 12, 13 are connected to the inputs of the circuit 26 for determining the failed bits. The output of circuit 26 is connected to the control inputs of registers 12 and 15 and is directly connected to the input of the fault multiplicity determination circuit 28. The output of circuit 28 is connected to one input of the circuit with one input of the comparison circuit 29, with the other input another control output of block 17 is connected, and the output of circuit 29 is connected to block 18. The output of circuit 28 is connected to one input of the comparison circuit 30, to another input of which, as well as to the control inputs of blocks 17 and 24, is connected to another the output of the resistor is 10, and the output of the circuit 30 is connected to the block 18 and another input Registers 10. The device operates as follows.

The corresponding (s) page of accumulator 6 / - the accumulator 8 cell is tuned and the content of its contents changes to a code, the force n of which is determined by the maximum multiplicity of failures (the power n of the correction code means its ability to detect multiplicity errors from 1 to / g inclusive). For example, if the maximum multiplicity of the failures accumulator 6 in the cells / w of the page 6 is equal to and, then the power-correction code is equal to where the failure occurs (the failures at the cell / and tip 6 pages are the result of accumulation in these cells times of failures of multiplicity s). When detecting in any cell / -and. Of the accumulator 6 failure of the multiplicity k + s, which was expected, when in the cell containing the th-fold failure, the multiplicity s fails, / - cell 8 is rearranged to a code with force, equal to k + 2s, then when a failure is detected, the fe-f2s multiplicity is a code with a force of + 3s, etc. Rebuilding / of a cell 8 occurs any time in any cell of / th page of drive 6 A fault was detected, the multiplicity of which is equal to the strength of the corrective code used by the / page drive 6.

To refer to the cell / s of drive 6, the address of this cell must be recorded — at input 2 in register 1. At the same time, at the address recorded in register 4, the word that determines the strength of the used / is read from register cell 8. -and page drive 6 correction code. The word read from accumulator 8 enters register 10, after which blocks 17 and 24 are tuned to the code used.

When recording, the information word zo input 5 23 enters block 24, from the output of which the code word, through a block of schemes, is not occupied. enter into drive 6.,.,:.: ..

When reading a code word from / accumulator 6, it is sent to register 12, and: from its output

10 through the block of circuits “OR 14 - into block 17 (reading a code word from accumulator 6 and writing it into register 12 can be combined in time with reading a word from tip 8 and writing it into register 10). Block 17

15 determines the presence of an error in the word read.

If the error signal from block 17 is missing, the information word from its output through the OR 21 block is output to output 22.

20 If an error signal occurs, no information word is output to output 22. The reverse code for the contents of register 12 goes through the OR 25 circuit in the same cell of accumulator 6, and then reads

25 from drive 6 to register 13.

Circuit 26 identifies the failed bits of a cell by matching the contents of the same bits of registers 12 and 13. Circuit 28 determines the multiplicity of the place of failure,

30 which is compared by circuit 29 with an error rate determined by block 17, and by circuit 30 - with the contents of register 10.

In case of equality of the error multiplicity and the multiplicity of the place of failure, the reverse

5, the code of the information part of the code word recorded in the register 13 is issued via the block of the OR 21 circuits to the output 22 (using systematic codes, the allocation of the information part of the code word is not difficult). At the same time, at output 22, the correct information word is obtained.

Example. Let the code word 01001010 ... be written in the cell 6 of the accumulator 6 (the check digits are indicated by dots), and as a result of a triple failure occurring in it, for example, the code word looks like 1IN010 ... (in the underlined bits the information was distorted caused by a triple error). After zaaisi, the same cell of the accumulator 6 of the read code of the read word and its information part of the code word will be 10110101, which, after inversion in register 13, will give the correct information word 0100 1010.

If the error multiplicity is not equal (less than) the multiplicity of the failure occurring,

0 the reverse code of the information part of the code word is not received at output 22. The circuit 26 through the block “AND 27 prohibits the issuance from the register 12 through the block circuit“ OR 14 to the block 17 of the contents of the failed bits. Instead

5 of these bits to the block of circuits "OR through

the valve 15 connects the bits of the block 16 (as the block 16 can be used, for example, a counter). Block 16 begins to consistently produce possible combinations of zeros and ones (correction words), the number of bits in which is equal to the number of failed bits in cell 6. The operation of block 16 stops as soon as from block 17 to block 18 there is no error signal. After correcting the distorted code word, the information word from block 17 goes through the OR 21 to output 22 block.

The said correction of the distorted code word could be made in the case of equality of the error multiplicity and the failure rate, however, in order to improve speed, the return code of the KQ information part: .J word written in register 13 was used through the “ Or 21 on. out, 22. . ; ;

At the end of the reading, if the circuit. 30 will determine the equality of the multiplicity of the failure place and the strength of the code used, all information from the / -th page of the accumulator is output, circuit 30 provides for changing the contents of the register 10, after which blocks 17 and 24 are rearranged and the code whose strength is

5 units higher than the strength of its code; Further, the input of the information of the D ./.-. to page 6 of the accumulator 6 and the recording:;

If the failure rate is not; equal (mey)

strength of used terrible accumulator

6 corrective code specified operations

(the output of information from / to the accumulator 6 page, changing the contents of the register 10, etc.) is not performed, and / - the accumulator 6 page continues to use the old code.

Subject invention

A memory device containing a drive connected to the address register, a power register of the correction code, one output of which is connected to the inputs of the coding and decoding units and one of the inputs of the first comparison circuit whose output is connected to the control unit and the other input to the output of the multiplicity determination circuit and one of the inputs of the second comparison circuit, the other input of which is connected to the output of the decoding unit, the generation of correction words, the output of which is connected to one input of the distributor Nogo block others. input to the output of the AND block and the one of the code word registers, and output via the OR block of the decoding block, the definition of failed bits, whose inputs are connected to the outputs of the code word registers, and the output to the information input of the block The circuits "And to the input of the circuit for determining the multiplicity of failures, characterized in that, in order to increase the effective capacity of the device, it contains an additional drive, the address input of which is connected to the output register of the address register, and the bit input output - respectively to another output and the input of the force register of the correction code.

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