SU1043743A1 - Self-checked storage - Google Patents

Abstract

1. MEMORIZING COMPETITION WITH AUTONOMOUS CONTROL, containing its “accumulator, whose numerical inputs are connected to the outputs of the decoder of the line, the main and additional amplifiers, one of the outputs / and inputs of which are connected respectively to the main and additional terminals of the separate inputs and the output of the accumulator, and the control inputs are connected to the first output of the input and output unit of information, the coding unit, whose outputs are connected to the first inputs of the AND elements and the inputs of the register of check bits; the outputs of which are connected to one of the inputs of the control unit of the signal processor, the address decoder of the bits, one of the inputs and outputs of which are connected respectively to the second output of the information input and output unit and to one of the outputs and inputs of the main, numerical register, the other inputs and outputs of which connected, respectively, to the outputs and to the inputs of the main amplifiers and the inputs of the coding block, and an additional numeric register, the inputs and one of whose outputs are connected to all inputs and to the inputs of additional amplification lei and element outputs and | and the other outputs to other inputs of the pilot signal generator, the second inputs of the And elements connected to the first input of the input and output information block, which is the recording write break input device, the second and third inputs, and the third output of the information input and output block, respectively. and address inputs and information output of the device, characterized in that, in order to increase the reliability of the device by detecting and correcting the error in two adjacent rows of accumulator rows , the block for calculating address codes, modulo two adders group, first V V Iw modulo two adder and element OR are entered into it, the first inputs of modulo adders two of the first group of connections with the outputs of the control number No. controllers, first outputs - with the first entrances of su F1ator modulo two second-S swarm and third groups, whose outputs and second outputs of modulo-two adders of the first group are connected to the inputs of the OR element, the output of which is connected to the fourth input of the input and output unit; second inputs sum-: 9 mators modulo two groups are connected to the outputs of the address code calculator, one of the inputs of which is connected to the first input of the information input and output DO, and the other inputs and the second input of the first modulo two are connected to the other outputs of the address decoder Dov. 2. The device according to claim 1, which is based on the fact that the unit calculates | The address codes contain two second and third modulators, unit counters, logical blocks, and a NOT element whose input is connected to the first inputs of the logical blocks and is one of the block inputs,

Description

one of the inputs of the second and third adders modulo two and the first unit counter, respectively, are combined and are other inputs of the block, the output of the element is NOT connected to the other inputs of the second and third modulators two, the outputs of which are connected to the inputs of the second and third counters units , the outputs of the first, second and third counters of units are connected to the second and third inputs of the first, second and third logical blocks, the outputs of the second and third (modulo two) and inputs

the first unit counter are the outputs of the block,

3. The device according to PP.1 and 2, about t. It is understood that each logical block contains the fourth and fifth modulo-two adders, the first inputs of which are combined and are the first, the input of the block, and the AND element, the first and second inputs of which are the second and third inputs of the block, and the output; and the second input element And are connected to the second inputs of the fourth and fifth modulo-two adders, respectively, the outputs of which are the outputs of the block.

The invention relates to computing technology and can be used in the manufacture of an LSI memory with a large area of crystals as well as in memory systems of increased reliability. Memory devices with autonomous control are known that contain a drive and logic circuits framed that allow access to one of the memory elements of the storage device ij during writing and reading of information. The disadvantage of this device is low reliability. The closest in technical essence to the invention is a memory device with autonomous control, which contains storage drives whose number buses are connected to the outputs of the address decoder, main and additional discharge buses of the storage drive are connected to one main and additional tires of the respective writing amplifiers, the other tires of which are connected to the corresponding bits of the register of the main bits and the inputs of the coding block, the outputs of the coding block are connected to the same inputs of the elements AND and the inputs of the additional register connected to the first inputs of the syndrome calculation circuit, the second buses of additional write-read amplifiers are connected to the register of additional bits and the outputs of the AND elements, the outputs of the register of additional bits are connected to the other registers the main types of connections are connected with the decoder of the address of bits, one inputs of which are connected to the address bits of the device, the second inputs of the address decoder of the bits are connected with the first output b The second and third outputs of which are connected respectively to the control inputs of the write-reading amplifiers and to the output of the device, the first, second and third inputs of the information input-output unit are connected respectively to the input information buses, the recording resolution and the second inputs of the elements And with the crystal sampling bus 2j. The disadvantage of this device is in-. It is that it does not provide for the processing of information without the occurrence of two, in particular, a number of defective memory elements (33), which reduces the reliability of the device. The aim of the invention is to increase the reliability of the device by detecting and correcting errors in two located bits of the accumulator line. The goal is achieved by the fact that in the memory device with aBToHOMf JM control, containing the accumulator, the numerical inputs of which are connected to the outputs of the line address decoder, are and additional amplifiers, one of the outputs and inputs of which are connected respectively to the main and additional bit inputs and output of the storage device, and the control inputs are connected to the first output of the information input and output unit, the coding unit whose outputs are connected to the first inputs of the And and And elements the inputs of the register of control bits, the outputs of which are connected to one of the inputs of the pilot of the control signals, the decoder address of the bits, one of the inputs and outputs of which are connected respectively to the second

output block input and output information. coding from the outputs and inputs of the main numeric register, other inputs and outputs WHICH are connected respectively to the outputs and to the inputs of the main amplifiers and the inputs of the coding unit, and an additional numerical register. The inputs and one of the outputs of which are connected to the outputs and to the inputs of additional auxiliaries and the outputs of the elements And, and the other outputs to the other inputs of the pilot signal generator, the second inputs of the elements And are connected to the first input of the input and output unit, which is the input of the permission of the The device si, the second and third inputs and the third output of the information input and output block are respectively information and address inputs and information output of the device, the block for calculating address codes, modulo two adders, the first modulo two, and the OR element are entered, and the first inputs of the adders modulo two of the first group are connected to the outputs of the pilot of the control signals, the first outputs -. with the first inputs of modifiers modulo two of the second and third groups, the outputs of which are And, the second outputs of modulators modulo two of the first group are connected to the inputs of the OR element, the output of which is connected to the fourth input of the block. input and output information, the second inputs of modulators two groups are connected to the outputs of the block calculating address codes, one of the inputs is connected to the first input of the input and output information locale, and the other inputs and the second input of the first modulo two are connected to the other decoder outputs addresses of bits

In addition, the block for calculating address codes contains the second and three modules modulo-two adders, unit counters, logical blocks, and the element NOT, whose input is connected to the first inputs of logical blocks, and is one of the inputs: to the block. moreover, one of the inputs of the second and third adders modulo two and the first unit counter, respectively, are combined and different, the block inputs, the element output is NOT connected to the other inputs of the second and third modulo adders two, the outputs of which are connected to the inputs of the second and third unit counters respectively, the outputs of the first, second and third counters of units are connected to the second and third inputs of the first, second, and third logical blocks, the outputs of the second and third adders modulo dVs

and the inputs of the first unit counter are the outputs of the block.

In addition, each logic block contains the fourth and fifth modulo-two adders, the first inputs of which are combined and are the first input of the block and the AND element, the first and second inputs of which are the second and third inputs of the block, and the output and the second input of the AND connected to the second inputs of the fourth and fifth modulo-two adders, respectively, the outputs of which are the outputs of the block.

Fig. 1 is a functional diagram of the proposed device; figure 2 - the same. calculating address codes.

The proposed device contains a drive 1 with additional

0 bits 2, numeric inputs 3, main 4 and additional 5 bit outputs and inputs, the decoder address of the lines, the main 7 and additional 8 amplifiers with

5 inputs 9 and 10, respectively, main 11 and additional 12 numeric registers, coding block 13, elements 14, decoder 15 addresses of bits with inputs and outputs

0 16. In FIG. 1, other outputs 17 of an additional numeric register are indicated. The device also contains the driver 18 control signals, the register 19 control bit 5. Dov, the first group of adders 20 modulo two with the first input inputs 21 and the first outputs 22, the second 23 and the third 24-group adders modulo two. In figure 1. indicated

0 and the second outputs of the 25 adders of the first group. The device also contains an OR 26 element, the first cyNwator 27 iio module two with inputs 28 and 29, information input and output block 30 with outputs 31-34 and inputs 35-37 and block 38 for calculating address codes with inputs 39-41 and outputs 42 -44. The block for calculating address codes contains (FIG. 2) a second 45 and a third 46 adders

0 modulo two, the element is NOT 47, the first is 48, the second is 49, and the torite is 50 unit counters with outputs 51-53, respectively, the first is 54, the second is 55 and the third is 56 logical units

5 55 and the third 56 logical blocks, each of which contains the element And 57, the fourth 58 and the fifth 59 adders.

The counters of units 48-50 are intended to establish the absence of unit symbols and the presence of one unit symbol in a binary word. Therefore, with the number of bits in the ems word, each 48-50 counter will consist of one

5 and -in element ILIG: NOT, elements NOT and in-input logic elements OR NOT. The proposed device is as follows. The principle of operation of the device is based on the property of the Hamming code, which consists in the fact that the place of the column vector in the check pattern Np.k of the code that coincides with the control signal indicates unambiguously the position of this bit in the accumulator. Taking into account that K of the main vector-columns of the matrix H of the code should not contain zero numbers and binary numbers, on one of the positions of which is 1, they have such a matrix, the first & the bits of the column vectors of which will coincide with the codes of the addresses of all bits of the accumulator 1 matrix. To do this, each column vector of the check matrix is supplemented with two bits taking into account the marked condition. For an example, matrixN, 2 01010101 10000 00110011 01000 00001111 00100 11101000 00010 OOOOOOOO is shown. 00001 in the mode of recording information on the inputs of the decoder b (Fig. 1) the incoming address code of the polled line. In accordance with this, one of the inputs 3 of the drive is excited. At the same time, on the basis of the address code of the polled digit, arriving at input 40 and 41, and single signals at inputs 35 and 37, in register 11 and the selected bit, two are recorded on the information arriving at input 36. By K of the polled page taking into account the recorded in block 13, P additional rows are formed which, through elements 14, pass to the inputs 10 of the amplifiers 8. The code word consisting of P and 1 through bits, amplifiers 7 and 8 is written in the corresponding line on the letter 1. On this the write cycle is fixed. in the information reading mode, signals at inputs 35 and 36 are missing. As in the write mode, registers 11 and 12 enter the word stored in accumulator 1 in the search line. By By K read bits (there may be errors in the word), block 13 again plays P bits, which are written to register 19 Next, it is determined whether the polled bit is correct, i.e. appropriately recorded. To do this, a signal 5 is formed in the driver 18, zero only if there are no errors in the read code word. At the same time, block 38 establishes the correspondence of the disposition of the respondent’s disposition and its neighboring bits with the matrix H. column vector. The inputs to inputs 40 and 41 of the block 38 of the I bits of the address code of the interrogated digit in adders 45 and 46 (FIG. 2 ) form L bits of address codes located on both sides of the polled column of accumulator 1 by boiling and subtracting a single bit coming from the input of the NOT element 47. At one of the outputs of the 48-50 counters there is a single signal, if dah will be. one n Whether, and the second output signal at the same Vits in the presence of these bit rows one and only one unit. Blocks 54-56 produce two additional bits and at outputs 42-44 of block 38 are formed, the three vector-capital matrices whose sequence numbers will be the same as the questioned and adjacent bits of the polled word (we believe that there may be two of the three adjacent bits.) In adders 21 it is set (when adding the column vector of the polled bit k and signal 5), a qi error occurred in the bit being polled. If an error has occurred, the output signal of the Wits 25 is a single signal (zero digits are in all digits of the resulting amount. The outputs of adders 23 and 24 contain single symbols if the conditions 5 © K4®Ko 0 and 5® are respectively satisfied., Where ko and Kg means adjacent column vectors of the check matrix, and @ means modulo-two addition. In case of an erroneous polled bit, the output of the OR 26 element contains a single signal, which in the adder 27 inverts the bit received from the output 29 of the decoder 15. Correct information through block 30 post output device 33. If one or two other (non-readable) bits are defective in the polled line, they will be corrected when they are read from the accumulator 1. In case of failure of one of the additional bits 2, the output of the OR 26 element is never there will be a single signal, and all the read bits will pass unchanged to the device output. As an example, consider writing and reading an information word consisting of eight bits. Suppose, for example, taking into account the entry of the Mord symbol and the state of the remaining ZE of the main bits of the line 1, Word A 10110111 should be stored. Then, in the additional bits 2 lines, according to the check MaTpHueHi3 g, additional bits 10101 should be written code word 8 10110111 10101 is written to the polled string. Let us further read the word B 10101111 10101 (the defective bits are underlined) in the registers 11 and 12, when reading the character of the nth bit. Register 19 records five newly created by block 13 characters 01011. Shaper 18 forms a signal 5 11110. At inputs 40 and 41 of the decoder 15, the address bit code of the requested bit 100 is set (and in the fourth bit is read Oil). With the help of the code, binary numbers 01100, 00101, 00011 are formed at outputs 42-44 blocks 38, respectively (when reading the fourth bit, respectively, 00011, 01100, 01010). The bits coming from the outputs 42 of the block 38 in the adders 21 are bitwise with the signal S: 01100 + 11110 10010/0. The result of the accumulation sticks to the first inputs of adders 23 and 24, at the outputs of which, respectively, logical O and 1 are formed (at output 25, adders 21 are also O). A single character from the output of 28 elements OR 26 will invert in the adder 27 an incorrectly read bit: JJl to O. This will allow to get the correct information at the output 33 of the device. . Thus, the proposed memory detects and corrects the memory in a series of located bits of the interrogated row of the accumulator matrix compared to correcting only one error in the known device, thereby increasing the reliability of the memory, since the analysis of the statistics of the distribution of dejrToV on easily usable crystals The baseline showed that almost all (95%) double defects in the lines of the accumulators are located in adjacent discharges. At the same time, the redundancy of the proposed memory practically does not increase, since if, in a known device, with a matrix organization of a drive for an LSI, four, sixteen and sixty four K bits need to be placed on the chip, respectively, seven, eight and nine GE columns, then in the proposed device — eight, nine, and ten additional columns 2. i.e. Lish one more than in the famous. Note that if the double errors were corrected by known methods, then with the same useful capacitance of the crystals, the number of additional columns of DF2 would have to be increased. In the known device, the largest area of the crystal in comparison with other redundant schemes is occupied by the decoding unit (location defective bit). In the proposed device, the circuit for determining the defectiveness of the read bit (block 38, adders 21-24 and the element OR 2b) require at least no more chip area than the block in the known device to allocate them, which means that device reliability is achieved with virtually no increase in the crystal area and device complexity. However, the stable operation of the device in the presence of two defective WE will increase not only its reliability, but also the yield of BIS ZU in their production. The technical and economic advantage of the proposed device lies in its higher reliability achieved by detecting and correcting errors in two rows of located accumulator bits.

Claims (3)

1. A REMOVABLE DEVICE WITH AN AUTONOMOUS CONTROL, containing a drive, the digital inputs of which are connected to the outputs of the decoder addresses of the lines, the main and additional amplifiers, one of the outputs. · And the inputs of which are connected respectively to the main and additional ·? to the drive addresses of discharges, one of the inputs and outputs of which are connected respectively to the second output of the input and output information block and to one of the outputs and inputs of the main, numerical register, other inputs and outputs the inputs of which are connected respectively to the outputs and inputs of the main amplifiers and the inputs of the coding unit, and an additional numerical register, the inputs and one of the outputs of which are connected to the outputs and to the inputs of the additional · amplifiers and the outputs of AND elements and other outputs to other inputs of the control driver signals, and the second inputs of the elements AND are connected to the first input of the input and output information block, which is the recording permission of the device, the second and third inputs and the third output of the information input and output block are respectively the information and address inputs and the information output of the device, which is related to the fact that, in order to increase the reliability of the device by detecting and correcting errors * in two adjacent bits of the drive’s row, * · We are a block for calculating address codes, 'the adder groups are modulo two, the first adder is modulo two and an OR element, and the first inputs of adders | C modulo two of the first group are connected! ^ With the outputs of the control signal generator | C, first exits - with first * the moves of adders modulo two second, second and third groups, the outputs of which and the second outputs of the adders modulo two of the first group are connected to the inputs of the OR element, the output of which is connected to the fourth input of the input unit and output. • information, the second inputs of the adders modulo two groups are connected to the outputs of the address code calculation block, one of the inputs of which is connected to the first input of the input and output information block, and the other inputs and the second input of the first adder are modulo two, connected to the other outputs of the digit address decoder. 2. The device according to claim 1, wherein the block for calculating address codes contains a second and third adders modulo two, unit counters, logical blocks and a NOT element whose input is connected to the first inputs of the logical blocks and is one of the inputs of the block, _ „> moreover, one of the inputs of the second and third adders modulo two and the first unit counter, respectively, are combined and are other block inputs, the output of the element is NOT connected to the other inputs of the second and third adders modulo two, the outputs of which are connected to the inputs of the second and third unit counters, respectively , the outputs of the first, second and third unit counters are connected to the second and third inputs of the first, second and third logic blocks, the outputs of the second and third adders are modulo two> and the inputs of the first counter Dinits are the outputs.₍ 3. The device according to claims 1 and 2, characterized in that each logical unit contains a fourth and fifth adders modulo two, the first inputs of which are combined and are the first, the input of the unit, and the element And, the first and second inputs of which are the second and the third inputs of the block, and the output and the second input of the element And are connected to the second inputs of the fourth and fifth adders modulo two, respectively / the outputs of which are the outputs of the block.