SU1417041A1 - Redundancy storage - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices. The purpose of the invention is to increase the reliability of the device. The device contains a memory block, an address register, a data register, an information analysis block, a control block, input and output switches, and a control block. The device uses a fourfold reservation. 3 hp f-ly, t Il.,. 1 tab.

Description

g (L

This invention relates to computer technology, in particular to memory storage devices.

The purpose of the invention is to increase the reliability of the device.

The drawing shows a block diagram of the device.

The device contains a memory block 1 having information capacity four times higher than that required for solving problems, the address register 2, the data register 3, the read information analysis block 4, the control block 5, the input 6 and output 7 switches, the control block 8.

The device also has a setup input 9, a write-read input 10, circulation input 11, address 12 and information 13 inputs, information outputs 14, output 15 End of circulation, output 16 Reliable information, output 17 Error has occurred.

The input 6 and output 7 switches are completely identical and contain each n + k data switching blocks 18 (n is the data size, k is the number of data bytes) and data bus 19.

Unit 5 contains a delay element 20, a decoder 21, a two-bit counter 22, a first 23, a second 24, and a third 25 OR elements.

Block 4 contains a parity control block 26, the first 27, second 28, third 29 and fourth 30 AND elements, the first 31 and second 32 OR elements, NOT-AND element 33, NOT 34 element. 1 Control block B contains n + k completely 35–35p identical control units, with nodes 35d and 35 lt I

control, the rest are informative, counter 36, comparison block 37, element OR 38, trigger 39, element NO 40, first 41, second 42 and third 43 elements I. Each of the switching blocks 18 contains the first 44 and second 45 elements AND- NOT, first 46 and second 47 elements AND, element OR 48.

The device works as follows.

Each time the device is accessed by the setup signal from input 9, registers 2 and 3, counter 22, flip-flops 39, counters 36 are reset (after the elements OR 32 and AND 42, and then it will be recorded in registers 2 and 3

five

0

five

respectively, address codes and input data (inputs 12 and 13. After setting at the inputs of each VIS memory (not shown) of block 1, the address code from the outputs of register 2 and counter 22, as well as a sign of writing or reading from input 10, an arithmetic unit (not shown) produces an equalization signal that, from input 11, through the OR element 24, enters the chip select input of each LSI of block 1. This records the information to the corresponding address of the first quarter of block 1 or reads the information from the corresponding address. the cycle time for accessing block 1, the address of the second quarter of block 1 of the same name is accessed, since the control signal delayed by the delay element 20 controls the counter 22 to the next state through the IL 23 element, and then OR 24 goes to the chip select inputs of all the LSIs of the block 1. In a similar way, the signal delayed by the delay element 20 calls the third and fourth quarters of the block 1. The code depends on the outputs of the counter 22 in each of the four device operation cycles selected one of the outputs of the decoder 21, which controls the operation of the input 6 and output 7 switches in such a way that in the recording mode in the first and third cycles to the inputs of block 1 through the elements 46 and 47 and the element OR 48 is fed from the bus 19 my code, in the second and fourth clock cycles through AND 44 and 45 elements and the OR 48 element is a reverse code. Similarly, when reading to the inputs of block 8, it is fed from block 1 through the output switch 7 to the direct code in odd clock cycles, and the reverse to the even code. In addition, the switches 6 and 7 connect the data bits to the inputs of block 1 and to the inputs of block 8, so that in each one-bit LSI information of two information bits is stored.

Table B shows an example of the placement of information in block 1 provided by switches 6 and 7.

5 Depending on the specific use of block 1, any other order of placement of information in it can be carried out by connecting

0

five

0

five

314

to the inputs of the switching unit 18 of data of various combinations of data bus bits (but the same for switches 6 and 7).

By placing information of each bit in different parts of the VIS pair and recording it in the direct code in two quarters of the same LSI and in the inverse code in the other fourths of the same LSI, it is possible to fully control the correctness of the information readable and its corrections, including the use of check bits with the convolution recorded in them modulo two for each byte.

Consider further the procedure of control and error correction.

1, All LSIs included in block 1 are intact. In each clock cycle, the information from the output of block 1 through the output switch 7 is fed to the input of each of the nodes 35. In each node 35, through the information element 41, O or 1, is fed to the input of a double-bit counter 36. At the expense of the control input, the block 37 comparison makes the comparison operation only in III and IV cycles with the corresponding delay for the time of information sampling. If all the LSIs are in good condition, then the output of the counter 36 will set after the third cycle the code 00 or 11. The signal from the output of the block 37 through the OR element 38 triggers the trigger 39. At the same time through the element NOT 40 to the input of the elements And 41 receives a signal prohibiting the flow from block 1 to the input of the counter 36 information in the next cycle. The information at the outputs of the higher bits of the counter 36 all corresponds to the true one. Since the triggers 39 of all bits worked, the read enable signal is set at the output of the And 27 element. Upon completion of the IV cycle, output 15 sets the End of Access signal.

In block 1 there are failed LSIs with any kind of failure, up to the complete inoperability of the whole LSIs. The number of failures completely BIS can reach half of all BIS block 1.

The principle of operation of each node 35 remains the same as that described in the previous paragraph. The difference is that by the end of the third

7041

tact in nodes 35 corresponding to defective LSI, codes 10 or 01 are set at the outputs of counters 36. At-THIS, the high and low bits of counter 36 are not compared in block 37, at least one of the triggers 39 does not work at output 16 Reliable in 10 Formali In the fourth cycle, the counters 36 corresponding to the healthy bits do not change their state, as shown above, and in the faulty nodes 35 in the meter 36, the code 11, 01 or 10 is written depending on the nature of the defects. code 11 is compared and the discharge operation in the fourth cycle is similar to that described in n, 1 for the third cycle. With

20, code 01, in the fourth cycle, the true information in this bit is O, i.e. true information is set at the corresponding output 14. In order to ensure the output of the signal to the output 16, the trigger 39 is switched by this bit along the circuit: AND 43, controlled by the low-order discharge of the counter 36 and the fourth clock signal delayed by

30 is the sampling time with the required delay, the OR element 38. Thus, if code 10 does not appear at the output of the counters 36 in any of the nodes 35, the corresponding signal appears at the fourth clock output at the output 16, and which is confirmed by the majority principle. The accuracy of the information in the control digits modulo two in this case is not taken into account.

35

40

five

0

five

After the fourth clock cycle, at the outputs of the counter 36 of at least one of the nodes 35, code 10 may occur. The reason for the appearance of such a code is the complete failure of an LSI pair of one bit per byte. Since the first quarter of one IPS recorded the direct code, the second - the reverse one, three third quarters of another LSI of this bit were also recorded directly, and the fourth - the reverse code, then almost every type of LSI failure up to the full of four quarters of this in the worst case, the LSI pairs are considered to be two 1 and two O, which determines the code 10 at the output of the counter. For the correction of such defects, the control method modulo two read information is used, which after

51

the fourth clock cycle is recorded in the higher bits of all counters 36. Since each associated LSI pair (e.g., 1 and 10; 2 and 11, etc.) is used simultaneously in the information bits of two bytes, it is necessary to have a check bit for each byte. First, a check is performed on the health of these bits. If the trigger 39 of one of the two test bits did not work in the fourth cycle, then at the output of the element I 23 and at one of the inputs of the element NE-33 would be O. Since the device has at least one faulty discharge of the counter 36 with code 10 on Since the element code 27 and, therefore, the input element NE-33 is O, then, after the input to the input, the held signal of the fourth cycle at the output of the element NOT-33 (on

the input of the element OR 31) input 1, which being passed to output 16

I indicates an uncorrectable error signal.

If both of the control bits are valid, but the control modulo two by block 26 does not detect an error, then there is a multiple error in two bytes. In this case, through the AND 29 and OR 31 elements, the output 17 also sets the error signal of the uncorrectable error. If the modulo two control detects an error in one or two bytes, then the error sigal is fed to the input of the AND 30 element and if there is a check-check health signal at the other input, and the third input of the delayed signal of the fourth clock cycle passes through the OR 32 element inputs of all information nodes 35 (except control). This signal is fed to the input of each element And 42 and does not affect the healthy bits, as. To the other input of each element 42, 1 is output from the corresponding trigger 39, inverted in O by the HE 40 element. In the faulty discharge, the output of the trigger 39 has O, so the other input of the And 42 element will be 1 and the counter 36 will reset to its original state 00. This is tantamount to adding in an irregular discharge, i.e. addition to the parity of the byte, since after the code is set in the faulty bit, after correction of the code 00,

170416

the trigger 39 of this bit, and then the element AND 27 and the output 16 turns on a signal that permits reading.

The proposed device maintains operability with a large number of failures included in the memory unit of the BIS memory, regardless of the nature of these failures (failures of individual restoring elements, rows, columns, input and output circuits up to failure of several complete LSIs).

five

0

five

0

five

0

five

0

five

Claims (4)

1. Redundant memory device, containing a memory block, data register, control unit, input and output switches, read information analysis unit, address register and control unit, the first address inputs of the memory unit connected to the output of the address register whose information inputs are the address inputs of the device, the information inputs of the memory unit are connected to the outputs of the input switch, the information inputs of which are connected to the outputs of the data register, the information inputs of which are and the informational inputs of the memory unit are connected to the information inputs of the output switch, the outputs of which are connected to the information inputs of the control unit, the outputs of the first group of which are the information outputs of the device, the first output of the control unit is connected to the second address input of the memory block, the second output the control unit is connected to the memory input of the memory unit, the third output of the control unit is connected to the control inputs of the input and output switches, the fourth output One control unit is connected to the first control input of the read information analysis unit and is an output of the device's access, the fifth output of the control unit is connected to the second control input of the read information analysis unit, the setup inputs of the register, data register, control unit, the read information analysis block and the control block are combined and are the installation inputs of the device, the write-read input of the memory block and the fourth control input of the analysis block 714 The read information 1 and 1 are combined and are the write / read input of the device, the control input of the control unit is the device access input, the outputs of the second group of the control unit are connected to the inputs of the first group of the read information analysis unit, the first output of the read information analysis unit is Reliable information devices, characterized in that, in order to increase the reliability of the device, in it the first, second and third control inputs of the control unit are connected respectively to the sixth and seventh outputs of the unit control and the second output of the read information analysis block, the third output of which is the output Device error is faulty, the information and control inputs of the read information analysis block are connected respectively to the information outputs of the device and to the outputs of the third group of the control block, the outputs of the fourth group of which are connected to - by the inputs of the second group of the block of analysis of the information read 2. The device according to claim 1, characterized in that the block of analysis of the read information contains from the first to the fourth elements AND, the first and second elements OR, the element NOT-AND, the element NOT, the control unit for parity, the first output of which is connected to the first the input of the third element And, the output of which is connected to the first input of the first element OR, the second input of which is connected to the output of the element NOT-AND, the inputs of the element NOT-AND connected respectively to the outputs of the element NOT, the first element AND, to the output of the second element AND The first input fourth element And, the second input of which is connected to the second output of the control element is parity, the output of the fourth element AND is connected to the first input of the second element OR, and the inputs of the first and second groups of the parity check block are respectively the information and control inputs of the block, the second input of the third element And the element input is NOT connected and is the first control input of the block, the second, third and fourth control inputs of which are respectively the third input 7041.8 the fourth AND element, the second input of the second OR element, and one of the inputs of the first AND element, the other inputs of which are the control inputs of the first block group, the code of the first AND element, the output of the second OR element, and the output of the first OR element, respectively, the first and the third outputs of the block, the inputs of the second element And are the control inputs of the second group of the block. 3, The device according to claim 1, wherein the control block contains n information and k control nodes (where n is the data size, k is the number of bytes in the data word), and the information inputs of the control nodes are The Q information inputs of the block, the first, second and third control inputs of the control nodes are respectively combined and are the first, second and third control inputs of the control unit, the control inputs of the control nodes are combined and are the installation input of the block, information and control outputs control information nodes are respectively 0, the outputs of the first and second groups of the block, the information and control outputs of the control nodes of the control are respectively the outputs of the third and fourth groups of the block. 4. The device according to claim 3, characterized in that each control node contains the first, second and third elements AND, a counter, a comparison unit, an element OR, an EQ. A NOT, whose code is connected to the first inputs of the first and second AND elements, the outputs of which are connected respectively to the counting and installation inputs of the counter, the outputs of the bits of the counter are connected to the information inputs of the comparison unit, the outputs of the third AND element and the comparison unit are connected to the inputs of the OR element, the output of which is connected to the trigger information input, output The low bit of the counter is connected to the first input of the third element And, the trigger output is connected to the input of the element NOT and is the control output of the node whose information output is the high discharge output of the counter, the second input of the third element, the control input of the comparison unit and the setting input Trig5 five 0 55 9141704110 Gera are respectively the first, - And the elements of AND are the respective second and third control inputs of the information and installation node, the second inputs of the first and the second inputs of the node. I my IIinversion. III my. IVinverse 123456789.1011 12 13 1A 15 16 17 18 1234567891011 12 13 14 15 16 17 18 10 11 12 13 14 15 16 17 18i23456789 10 11 12 13 14 15 16 17 18, l 23456789