SU1587600A2 - Dynamic memory with error corrections - Google Patents

Abstract

The invention relates to computer technology, in particular to storage devices, and can be used as a random access memory with error correction. The purpose of the invention is to reduce the recovery time of the device by introducing into it a block of formation of failures and its implementation on the AND elements, the counter and the HE element. This allows not only to extract failed memory cells, but also to output their addresses to the processor. 1 hp f-ly, 2 ill.

Description

The invention relates to computer technology, in particular, to storage devices, can be used as an operative memory with error correction, and is an improvement of the device according to the main author, 1133625.

The purpose of the invention is to reduce the recovery time of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - functional block failure detection circuit.

The device (Fig. 1) contains a drive 1, a counter 2, an address register 3, switches 4 and 5, a control block 6, a block for fixing failures, a driver 8 for control signals, a register 9 for regeneration, a correction block 10, a decoder 11, an address 12 and information 13 device inputs, control inputs 14-16 and device outputs 17-19. Block 7 of the fixing of failures contains elements And 20-22, counter 23 and the element NOT 24.

The device works as follows.

At input 15, a synchronizing series enters the second input of control unit 6. The memory access signal is fed to the input 14 to the first input 9 of the control unit 6. The frequency of the sync series is three times the frequency of the arrival of the inversion signals. When a signal arrives Recording on input 16 to the third input of control unit 6 on the first and second outputs there appear unit levels that go to the control inputs of accumulator 1 and which are used to record information.

If a Read (zero level) signal is given at input 16, then a single level appears only at the second output of block 6, which is fed to the corresponding input of accumulator 1 and under the influence of which information is read.

On the second clock pulse, the unit level appears only at the second input of the control unit 6, which is fed to

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The corresponding input of the drive 1 and reads the information. In this case, the regeneration, reading and control of information takes place. In this cycle, if an error is detected at the second output of the correction unit 10, a single level will appear that goes to one of the inputs of the AND 21 element, the input of the counter 23 and the input of the AND 20 element. Since the counter 23 counts up to two, then at its output the zero level remains that goes to the output of the NOT 24 element. At the output of this element, the unit level causes the information to be re-read from accumulator 1. When an error is detected, it is repeatedly assumed that the memory cell in the accumulator failed. The error signal from the second output of the correction unit 10 is fed to one of the inputs of the 1/1 20 element. Now, at the output of the counter 23, there appears a unit level that goes to the input of the And 22 element, the input of the HE element 24, the input of the And 21 element and output 19 of the device. From the output of the element And 21 through the second output of the block 7 for fixing failures, the unit level is fed to the corresponding input of the block 6

management

In this case, single levels appear on the first and second outputs of the control block b, which are fed to the control inputs of the accumulator 1 m and record information.

Thus, the circulation gap is divided into three clocks. The first one records or reads information, the second one regenerates and reads information to control it, the third one writes the corrected information to the memory, if errors were detected in the previous step when re-reading. The first clock pulse on the second input of unit 6 forms a unit level at its third output and provides connection via switches 4 and 5 to the address and information inputs of drive 1 of the corresponding signals. The zero level of this signal connects, respectively, the output of the counter 2 and the output of the register 9 of regeneration. The leading edge of this signal adds one to the contents of counter 2.

In the write cycle, the input 13 is supplied with information to be written to the drive 1. In the driver 8 control signals. In addition, the formation of additional bits of the Hamming code to detect and correct single errors occurs. From the output of the block B, the information bits and bits of the Hamming code are fed to one of the inputs of the switch

5 10

5. E, the cynical signal from the third output of the control unit 6 connects through the first switch 4 to the address inputs of the accumulator 1 and to the input of the decoder 11 the contents of the register 3 address, and through the second switch 5 to the information inputs of the accumulator 1 connects the outputs of the imager 8. Under the influence of signals from the corresponding outputs of block 6 in the feeder 1, information is recorded.

In the read cycle from input 12 to the input of register 3 of address 2, the code addresses come in, from input 14, the access signal and from input 16, the read signal. The work of the address part 5 is similar to the write cycle. Under the influence of the control signal from the second output of the control unit 6 in the accumulator 1, information is read at the address received from register 3. The read bits 0 of the information and the bits of the Hamming code go to correction block 10, where, if a single error is detected, it is corrected and output to output 17. At one time, this information is entered into the regeneration registrar 9 registry 9. The error signal from the corresponding output of block 10 is fed to the input of block 7, in which the repeated access is made to drive 1. If it is again found again during error reading, then the address is allowed to exit from the output of register 3 of the address,

If the error is not detected when re-reading, then the zero level from the output of the correction block 10 goes to the 35 input of the block 7 and closes it, preventing the organization of reading the information

time.

In the second cycle, the zero-level control unit 6 at the third output connects through switch 4 to address inputs of accumulator 1 and inputs of decoder 11 the contents of counter 2, as a result of which information from accumulator 1 is read into correction block 10. With the corresponding 45th output of the correction unit 10, the corrected information is recorded in the regeneration register 9. If an error is detected, the correction block 10 outputs a signal to the input of block 7. The operation of block 7

.50 is similar to the previous beat.

Thus, in the device being prelagged, the failure of memory cells is detected and the address of the failed cells is output to the processor. The issuance of the address of the failed cell to the indication allows for corrective action, i.e. reduces recovery time, which in turn leads to an increase in device availability.

Claims (1)

1. Dynamic storage device with error correction by aut. St. 1133625, characterized in that, in order to reduce the recovery time of the device, a fail-over block was inserted into it, the address input of which is connected to the output of the address register, the second output of the correction block is connected to the control input of the fail-safe block, the first output of which connected to the second control input of the accumulator, the fourth input of the control unit is connected to the second output of the fail-safe block, the third and fourth outputs of which are the second and third outputs of the device. 2, The device according to claim 1, characterized in that the block for fixing failures contains AND elements, a counter and an NOT element, the output of which is connected to the first input of the first AND element, the second input of the first AND element is a control the input of the block of fixing of failures and connected to the first input of the second element I and with the counting input of the counter, the output of which is the fourth output of the block of fixing of failures and connected to the first the input of the third element is AND, with the second input of the second element is AND and the input of the element is NOT, the output of the first element is AND the first output of the block fixing failures, the output of the second element AND is the second output of the block fixing failures, the second input and output of the third element AND respectively, the address input and the third output of the block for fixing failures. L Js 2tf C A23 FIG. 2